CCM: Changing clock parent freezes system

[wolfgang_baer]

Hi,

we have an imx8md processor on a custom board and we need to use CLK_EXT3 as input to one of the SAI modules.

However if we change the assigned parent in the device tree the board freezes without any error during boot up:

&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_EXT3>;
status = "okay";
};

If I change the clock parent to any other (e.g. 25M_REF_CLK or IMX8MQ_AUDIO_PLL1_OUT) of the supported clock parents according to reference manual it works. 

The pins are configured as required:

pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x00000011 
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x00000011

The same applies to clock slice 117 IPP_DO_CLKO2 if I try to reparent to anything other than the default 25M_REF_CLK. The system instantly freezes without any error.

If I change the above from userspace via the CCM registers the same happens -> freeze:

Set CLKO2 to 32K reference clock: devmem2 0x3038BA84 w 0x17000000

The reference manual does not mention anything regarding these topics or if there is a special sequence etc.

which must be followed to change parents. 

Any help or hints are appreciated!

Thanks,

Wolfgang

[wolfgang_baer]

Hi Igor,

thanks for your fast reaction.

We found the root cause in a malfunction in the FPGA generating the clock for CLK_EXT3. After fixing, the clock was generated correctly and we could switch to the CLK_EXT3 without freezing.

However, this opens two more questions on my side.

1) I was hoping that we can switch parents also without a clock available at the EXT pin as long as we do not

    ENABLE that clock. This seems not to be the case. There are times the FPGA will be reconfigured.

2) The GPR_SAI2_EXT_MCLK_EN register you mentioned. There is no documentation - only the name of the register.   

    The usage of the EXT_CLK for SAI seems to work without that register set. At least for the above described case.

   Can you give some hint what this register actually is supposed to do / control?

Thanks a lot for your help and sharing your expertise,

Wolfgang

[igorpadykov]

Hi Wolfgang

SAI2 MCLK  can be selected from SAI2_CLK_ROOT from CCM or SAI2 MCLK from IOMUX.
GPR_SAI2_EXT_MCLK_EN=1 enables usage SAI2 external MCLK, from IOMUX.

GPR_SAI2_EXT_MCLK_EN=0, enables usage SAI2 internal MCLK,  from CCM
configured by MSEL field - Selects the audio Master Clock option used to generate an
internally generated bit clock. Described in sect.13.8.4.1.6 SAI Transmit Configuration 2
Register (TCR2) i.MX8MDQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

please describe in more details these new questions and

provide steps how these issues can be reproduced on i.MX8M EVK

reference board with official NXP linux BSPs on

linux-imx - i.MX Linux kernel 

Best regards
igor

[igorpadykov]

Hi Wolfgang

one can check GPR_SAI2_EXT_MCLK_EN described in

sect.8.2.4.3 GPR2 General Purpose Register (IOMUXC_GPR_GPR2)

i.MX8MDQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

Best regards
igor
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