Explenation for HS-SETTLE parameter in MIPI CSI D-PHY registers

[robrechtbisscho]

Hello,

I am currently working on modifying the OV5640 mipi driver so it can work for our custom camera sensor on the SABRE board. In the device tree of the sabre board there is the following configuration:

&mipi_csi {
     clock-frequency = <240000000>;
     status = "okay";
     port {
     
          mipi_sensor_ep: endpoint1 {
               remote-endpoint = <&ov5640_mipi_ep>;
               data-lanes = <2>;
               csis-hs-settle = <13>;
               csis-clk-settle = <2>;
               csis-wclk;
          };

          csi_mipi_ep: endpoint2 {
               remote-endpoint = <&csi_ep>;
          };
     };
};‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I can see in the driver that the csis-hs-settle and csis-clk-settle parameter set the corresponding parameters in the  MIPI_CSI2_DPHY_CMN_CTRL  register. In the datasheet however, there is no mention what these values actually mean. Since the Ths-settle time of the receiver on the PHY is a very critical parameter to get the MIPI working i would like to know what the meaning of this value 13 is. Anybody any idea?

Also it is not clear to me what clock-frequency parameter exactly does. If i look into the driver, i see that this sets the mipi_clk. When i measure the clock on the mipi clk lane for the OV5640, i measure a frequency of 112MHz. So i don't understand why you would need to set the D-PHY mipi clk to 240Mhz. Does this have to be in a certain range so that the PHY can lock on the mipi clk?

Thanks for your help.

[dh29]

Hi Robert,

I am working on integrating an Analog-Devices ADV7280M with an iMX7 based SOM over its CSI-MIPI. I have this working, but I don't like using values 'pulled from thin-air', hence I have been asking the same questions as you did.

NXP have pointed me at this post, and the HS-SETTLE table (missing from the iMX7DRM manual !!) has helped in my understanding.

However, I am still struggling with the concept of the WRAP_CLK ?? NXP-support is refusing to answer any further questions regarding this - which is not very helpful considering the iMX7's documentation is the poorest I have seen in 25+ years of embedded design. [Our next design will not be using NXP].

NXP state that “csis-wclk is external clock to CSI-MIPI”. I can see that this device-tree entry controls BITS 3,2,1,0 of register MIPI_CSI2_CSIS_CLK_CTRL and this determines the source of the PIXEL_CLOCK, BUT why should I choose EXTCLK (WRAP_CLK) instead of PCLK ??? 

Section 13.5.3.11.1 of iMX7DRM manual states that the I_WRAP_CLK is up to 200MHz. BUT what is its source? How is it configured? How do I know it is within the 200MHz limit?

Any explanation would be very appreciated.

[qiang_li-mpu_se]

Hi dh29,

The PCLK is the internal clock from MIPI CSI2 module to CSI module, it has two clock source:

0=I_PCLK, this clock source is from APB_CLK

1=EXTCLK, this clock source is from MIPI_CSI_CLK

Based on different camera input, the PCLK frequency will be different, so we suggest to use the 1=EXTCLK, the driver can modify the MIPI_CSI_CLK clock easily. APB_CLK is bus clock related, change its frequency will impact the system.

Since this clock is sent to IMX7D's CSI module, there is limitaion in CSI side. The 200MHz limitation is coming from here.

[dh29]

Hi Qiang_FSL 

This has helped me to understand the different MIPI clock terminologies and explains why I should use EXTCLK (WRAP_CLK, csis-wclk).

Many thanks.

[qiang_li-mpu_se · Accepted solution]

For "clock-frequency = <240000000>;", it is used to set the MIPI CSI host's working clock, MIPI_CSI_CLK_ROOT. You don't need modify it.

A table for MIPI clock frequency and register setting of HSSETTLE[7:0] and CLKSETTLECTL[1:0] had been missed in iMX7D reference manual.

MIPI Serial clock Frequency (MHz)	HSSETTLE[7:0]	CLKSETTLECTL[1:0]
1500	33	0
1490~1450	32	0
1440~1410	31	0
1400~1360	30	0
1350~1320	29	0
1310~1270	28	0
1260~1230	27	0
1220~1180	26	0
1170~1130	25	0
1120~1090	24	0
1080~1040	23	0
1030~1000	22	0
990~950	21	0
940~910	20	0
900~860	19	0
850~820	18	0
810~770	17	0
760~730	16	0
720~680	15	0
670~640	14	0
630~590	13	0
580~550	12	0
540~500	11	0
490~460	10	0
450~410	9	0
400~370	8	0
360~320	7	0
310~280	6	0
270~230	5	0
220~190	4	0
180~140	3	0
130~100	2	0
90~80	1	0

[michaeltang]

Hi Qiang_FSL‌, 

What if the MIPI clock running at 402MHz (pixel rate 804Mbps), should I use 8 or 9 for HSSETTLE?

I'm porting a new camera to i.MX8M and finding any suitable document for the clock settings of MIPI IP, thanks!

MIPI Serial clock Frequency (MHz)	HSSETTLE[7:0]	CLKSETTLECTL[1:0]
450~410	9	0
400~370	8	0

[qiang_li-mpu_se]

iMX8M MIPI CSI2 PHY is different to iMX7D.

For iMX8M CSI2_1_S_PRG_RXHS_SETTLE setting, please reference to followed table:

[ToarteFretter]

Hi,

We're currently also in the progress of starting up the MIPI-CSI2 interface (not using any Linux) on an i.MX8QM, and are struggling (again) with the very unclear documentation (or absence of it).

We have a few questions:

1) Where can we find the referenced tables 34 and 35; is this from some other i.MX8 reference manual, or application note, or an NXP internal document?

2) When reading the NXP AN13573 document, we were under the impression that "UI" was the period of the clk_ui, being the outgoing pixel clock of the MIPI block (pixel link as such)? Even though that we're wondering if this was making any sense; since this pixel clock has nothing to do with the D-PHY. However, the referenced table 35 uses for UI the period of one bit time (bit rate) on the MIPI lane(s), which seems to make more sense. Can it be confirmed that AN13573 is incorrect in the example shown in 6.1.5 (or is at least very misleading), where for UI rather the SoC generated clk_ui period is used which doesn't have a direct relation (and is even not in the same order of magnitude) with the bit rate on the MIPI lane(s)?

3) We only have one MIPI-CSI2 lane being used today, but in case we would have 2 or 4 lanes, what would be the impact on the setting of S_PRG_RXHS_SETTLE? If the setting is related to the lane bitrate, the setting should be the same for more lanes if the MIPI lane frequency is still the same? If the setting is indeed related to the generate clk_ui pixel clock, then the setting should change because there are more pixels to transfer within a given time period, hence a shorter pixel time? Which one of the options is correct?

Thanks.

Regards,

Toarte fretter.

[Amal_Antony3331]

Hi @qiang_li-mpu_se 

I am trying to integrate mipi camera(IMX219) to our IMX8MP custom board. I have to connect four IMX219 modules to iMX8MP. But it is having only 2 CSI interfaces, I'm doing it using an i2c MUX and two MIPI switches.

I'm able to get the stream from the CSI0 interface(both channel 1 and channel 2). But not with CSI1 interface (Channel 3 and channel 4). Getting the following error upon accessing the channel 3.

ERROR : [MediaPipeline] NativeSensor open error!
ERROR : [V4l2Event] initialize MediaPipeline error!

/dts-v1/;

#include "imx8mp-evk.dts"

&i2c3 {

clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";

/delete-node/ov5640_mipi@3c;

pca9849: pca9849@71 {
compatible = "nxp,pca9849";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
powerdown-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
reset = <&gpio3 19 GPIO_ACTIVE_HIGH>;

i2c_0: i2c_0@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "okay";

imx219_0: imx219_0@10 {
compatible = "sony,imx219";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <0>;
pwdn-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";

port {
imx219_mipi_ep_0: endpoint {
remote-endpoint = <&mipi_csi_ep_0>;
data-lanes = <1 2>;
clock-lanes = <0>;
clock-noncontinuous;
max-pixel-frequency = /bits/ 64 <266000000>;
};
};
};
};
/*i2c_1: i2c_1@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "okay";

imx219_1: imx219_1@10 {
compatible = "sony,imx219";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";

port {
imx219_mipi_ep_1: endpoint {
remote-endpoint = <&mipi_csi_ep_1>;
data-lanes = <1 2>;
clock-noncontinuous;
clock-lanes = <0>;
max-pixel-frequency = /bits/ 64 <500000000>;
max-data-rate = /bits/ 64 <912000000>;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};*/
i2c_2: i2c_2@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "okay";

imx219_2: imx219_2@10 {
compatible = "sony,imx219";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <1>;
pwdn-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";

port {
imx219_mipi_ep_1: endpoint {
remote-endpoint = <&mipi_csi_ep_1>;
data-lanes = <1 2>;
clock-lanes = <0>;
clock-noncontinuous;
max-pixel-frequency = /bits/ 64 <266000000>;
max-data-rate = /bits/ 64 <912000000>;
link-frequencies = /bits/ 64 <750000000>;

};
};
};
};
/*i2c_3: i2c_3@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "okay";

imx219_3: imx219_3@10 {
compatible = "sony,imx219";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <1>;
pwdn-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";

port {
imx219_mipi_ep_3: endpoint {
remote-endpoint = <&mipi_csi_ep_3>;
data-lanes = <1 2>;
clock-lanes = <0>;
};
};
};
};*/
};

};

 

&cameradev {
status = "okay";
};

&isi_0 {
status = "disabled";
};

&isi_1 {
status = "disabled";
};

&isp_0 {
status = "okay";
};

&isp_1 {
status = "okay";
};

&dewarp {
status = "okay";
};


&mipi_csi_0 {

status = "okay";
clock-frequency = <266000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
assigned-clock-rates = <266000000>;

port@0 {
reg = <0>;
mipi_csi_ep_0: endpoint {
remote-endpoint = <&imx219_mipi_ep_0>;
data-lanes = <2>;
csis-hs-settle = <16>;
csis-clk-settle = <2>;
csis-wclk;
};
};

};

&i2c2 {
/delete-node/ov5640_mipi@3c;
};

&mipi_csi_1 {
status = "okay";

port@1 {
reg = <1>;
mipi_csi_ep_1: endpoint {
remote-endpoint = <&imx219_mipi_ep_1>;
data-lanes = <2>;
csis-hs-settle = <16>;
csis-clk-settle = <2>;
csis-wclk;
};
};
};

Attaching the dtsi file for reference.

Does it require any change to enable the second MIPI CSI interface?

Any help is appreciated.

Thanks in advance!

Regards

Charles

[michaeltang_ltc]

Hello @qiang_li-mpu_se ,

I'm developing the camera with i.MX8M Plus now, could you please to provide the `hs_settle` and `clk_settle` settings for our reference, thanks. 

[martinkepplinge]

hi qiang,

I can see how that table shows how to calculate Ths_settle (in ns) for any given data rate. How exactly do the register bits then relate to that value?

sorry in case I overlook something obvious. thank you in advance.

martin

[coindu]

hi：

        I use the IMX8MQ chip to inherit a camera, and need MIPI-CSI output 400M clock,  so how to set the value of csis-hs-settle and csis-clk-settle?

      Can you provide this manual which contains table 34 and table 35.

[martinkepplinge]

please also see how the mainline driver calculates hs_settle from the lane rate and esc clock: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/staging/media/imx/im...

[john_obendorfer]

Gents, I can't make any sense whatsoever out of this table:

1.  On the IMX8M, there is no 5-bit  "PRG_RXHS_SETTLE" parameter referenced anywhere in the IMX8M reference manuals.  Rather, there's a 7-bit HS_SETTLE parameter (bits 31-24 in the MIPI_CSI_DPHY_COMMON_CTRL register, see section 13.4.15.8 in the IMX8MMRM reference manual, revision 2.

2.  In Table 34 above, THS-settle is defined with a min value of 8ns + 6*UI.  What is "UI"?

3.  What is RxClkInEsc?  I can't find that term anywhere in the IMX8MMRM manual either.

4.  If we're running a data rate that is between the discrete Data Rate values listed in Table 35, do we interpolate an HS_SETTLE value?

A general comment to the support staff: your life will get MUCH easier if you can cajole NXP engineering into properly documenting the CSI2 and Bridge modules.

Thanks to anyone who can answer any of the above questions!

John

[qiang_li-mpu_se]

Hi John,

The above table 34 and Table 35 are for iMX8MQ, not for iMX8MM. The iMX8MM MIPI CSI2 should reference to iMX7D's. 

Table for HSSETTLE[7:0] and CLKSETTLECTL[1:0].

[tom_perman]

Hi,

I am also developing a product using the iMX8MM SoC, and hence this is very useful information. Can I request that this table is added to the official IMX8MM documentation (e.g Reference Manual)? I think this would reduce the amount of confusion regarding correct configuration. 

Thanks,

Tom 

[john_obendorfer]

Thank you for the clarification!

The "MIPI serial clock frequency" in the first column: is that a) the MIPI_CSI_CLK_ROOT frequency, or b) the MIPI clock lane frequency?  On our board, the device tree parameter "clock-frequency"  is set to 333MHz, while the MIPI clock lane is running at 1.188GHz.  I think the value I want to use in the table lookup is 333MHz, but thought should ask ... 

Thanks & Regards,

John

[qiang_li-mpu_se]

Hi John,

It should be the MIPI clock lane frequency * 2. So it follows the external MIPI CSI2 input signal. You don't need change the CPU internal MIPI_CSI_CLK_ROOT.

[john_obendorfer]

Thank you!

[robrechtbisscho]

Thank you for your answer. But it is still not clear to me however. In your table there is only the value 0 for CLKSETTLECTL while in the device tree value 2 is used.

I also assume that de MIPI clock in the table you provide is DDR? So when i measure a MIPI clock of 112MHz using a scope i would have to actually use 224MHz in the table?

I can not seem to map the used values in the device tree to the values in the table.

[qiang_li-mpu_se]

The table is for DDR mode, so your setting 224MHz is OK.

The CLKSETTLECTL setting is not important, the old BSP hasn't set it, just used the default register value 0.