Explenation for HS-SETTLE parameter in MIPI CSI D-PHY registers

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Explenation for HS-SETTLE parameter in MIPI CSI D-PHY registers

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robrechtbisscho
Contributor II

Hello,

I am currently working on modifying the OV5640 mipi driver so it can work for our custom camera sensor on the SABRE board. In the device tree of the sabre board there is the following configuration:

&mipi_csi {
     clock-frequency = <240000000>;
     status = "okay";
     port {
     
          mipi_sensor_ep: endpoint1 {
               remote-endpoint = <&ov5640_mipi_ep>;
               data-lanes = <2>;
               csis-hs-settle = <13>;
               csis-clk-settle = <2>;
               csis-wclk;
          };

          csi_mipi_ep: endpoint2 {
               remote-endpoint = <&csi_ep>;
          };
     };
};‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I can see in the driver that the csis-hs-settle and csis-clk-settle parameter set the corresponding parameters in the  MIPI_CSI2_DPHY_CMN_CTRL  register. In the datasheet however, there is no mention what these values actually mean. Since the Ths-settle time of the receiver on the PHY is a very critical parameter to get the MIPI working i would like to know what the meaning of this value 13 is. Anybody any idea?

Also it is not clear to me what clock-frequency parameter exactly does. If i look into the driver, i see that this sets the mipi_clk. When i measure the clock on the mipi clk lane for the OV5640, i measure a frequency of 112MHz. So i don't understand why you would need to set the D-PHY mipi clk to 240Mhz. Does this have to be in a certain range so that the PHY can lock on the mipi clk?

Thanks for your help.

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1 Solution
6,146 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

For "clock-frequency = <240000000>;", it is used to set the MIPI CSI host's working clock, MIPI_CSI_CLK_ROOT. You don't need modify it.

A table for MIPI clock frequency and register setting of HSSETTLE[7:0] and CLKSETTLECTL[1:0] had been missed in iMX7D reference manual.

MIPI Serial clock Frequency (MHz)HSSETTLE[7:0]CLKSETTLECTL[1:0]
1500330
1490~1450320
1440~1410310
1400~1360300
1350~1320290
1310~1270280
1260~1230270
1220~1180260
1170~1130250
1120~1090240
1080~1040230
1030~1000220
990~950210
940~910200
900~860190
850~820180
810~770170
760~730160
720~680150
670~640140
630~590130
580~550120
540~500110
490~460100
450~41090
400~37080
360~32070
310~28060
270~23050
220~19040
180~14030
130~10020
90~8010

View solution in original post

21 Replies
6,141 Views
dh29
Contributor IV

Hi Robert,

I am working on integrating an Analog-Devices ADV7280M with an iMX7 based SOM over its CSI-MIPI. I have this working, but I don't like using values 'pulled from thin-air', hence I have been asking the same questions as you did.

NXP have pointed me at this post, and the HS-SETTLE table (missing from the iMX7DRM manual !!) has helped in my understanding.

However, I am still struggling with the concept of the WRAP_CLK ?? NXP-support is refusing to answer any further questions regarding this - which is not very helpful considering the iMX7's documentation is the poorest I have seen in 25+ years of embedded design. [Our next design will not be using NXP].

NXP state that “csis-wclk is external clock to CSI-MIPI”. I can see that this device-tree entry controls BITS 3,2,1,0 of register MIPI_CSI2_CSIS_CLK_CTRL and this determines the source of the PIXEL_CLOCK, BUT why should I choose EXTCLK (WRAP_CLK) instead of PCLK ??? 

Section 13.5.3.11.1 of iMX7DRM manual states that the I_WRAP_CLK is up to 200MHz. BUT what is its source? How is it configured? How do I know it is within the 200MHz limit?

Any explanation would be very appreciated.

6,141 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

Hi dh29,

The PCLK is the internal clock from MIPI CSI2 module to CSI module, it has two clock source:

0=I_PCLK, this clock source is from APB_CLK

1=EXTCLK, this clock source is from MIPI_CSI_CLK

Based on different camera input, the PCLK frequency will be different, so we suggest to use the 1=EXTCLK, the driver can modify the MIPI_CSI_CLK clock easily. APB_CLK is bus clock related, change its frequency will impact the system.

Since this clock is sent to IMX7D's CSI module, there is limitaion in CSI side. The 200MHz limitation is coming from here.

6,132 Views
dh29
Contributor IV

Hi Qiang_FSL 

This has helped me to understand the different MIPI clock terminologies and explains why I should use EXTCLK (WRAP_CLK, csis-wclk).

Many thanks.

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6,147 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

For "clock-frequency = <240000000>;", it is used to set the MIPI CSI host's working clock, MIPI_CSI_CLK_ROOT. You don't need modify it.

A table for MIPI clock frequency and register setting of HSSETTLE[7:0] and CLKSETTLECTL[1:0] had been missed in iMX7D reference manual.

MIPI Serial clock Frequency (MHz)HSSETTLE[7:0]CLKSETTLECTL[1:0]
1500330
1490~1450320
1440~1410310
1400~1360300
1350~1320290
1310~1270280
1260~1230270
1220~1180260
1170~1130250
1120~1090240
1080~1040230
1030~1000220
990~950210
940~910200
900~860190
850~820180
810~770170
760~730160
720~680150
670~640140
630~590130
580~550120
540~500110
490~460100
450~41090
400~37080
360~32070
310~28060
270~23050
220~19040
180~14030
130~10020
90~8010

View solution in original post

6,141 Views
michaeltang
Contributor II

Hi Qiang_FSL‌, 

What if the MIPI clock running at 402MHz (pixel rate 804Mbps), should I use 8 or 9 for HSSETTLE?

I'm porting a new camera to i.MX8M and finding any suitable document for the clock settings of MIPI IP, thanks!

MIPI Serial clock Frequency (MHz)HSSETTLE[7:0]CLKSETTLECTL[1:0]
450~41090
400~37080
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6,141 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

iMX8M MIPI CSI2 PHY is different to iMX7D.

For iMX8M CSI2_1_S_PRG_RXHS_SETTLE setting, please reference to followed table:

01.jpg

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michaeltang_ltc
Contributor II

Hello @qiang_li-mpu_se ,

I'm developing the camera with i.MX8M Plus now, could you please to provide the `hs_settle` and `clk_settle` settings for our reference, thanks. 

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martinkepplinge
Contributor I

hi qiang,

I can see how that table shows how to calculate Ths_settle (in ns) for any given data rate. How exactly do the register bits then relate to that value?

sorry in case I overlook something obvious. thank you in advance.

martin

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coindu
Contributor IV

hi:

        I use the IMX8MQ chip to inherit a camera, and need MIPI-CSI output 400M clock,  so how to set the value of csis-hs-settle and csis-clk-settle?

      Can you provide this manual which contains table 34 and table 35.

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martinkepplinge
Contributor I

please also see how the mainline driver calculates hs_settle from the lane rate and esc clock: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/staging/media/imx/im...

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john_obendorfer
Contributor II

Gents, I can't make any sense whatsoever out of this table:

1.  On the IMX8M, there is no 5-bit  "PRG_RXHS_SETTLE" parameter referenced anywhere in the IMX8M reference manuals.  Rather, there's a 7-bit HS_SETTLE parameter (bits 31-24 in the MIPI_CSI_DPHY_COMMON_CTRL register, see section 13.4.15.8 in the IMX8MMRM reference manual, revision 2.

2.  In Table 34 above, THS-settle is defined with a min value of 8ns + 6*UI.  What is "UI"?

3.  What is RxClkInEsc?  I can't find that term anywhere in the IMX8MMRM manual either.

4.  If we're running a data rate that is between the discrete Data Rate values listed in Table 35, do we interpolate an HS_SETTLE value?

A general comment to the support staff: your life will get MUCH easier if you can cajole NXP engineering into properly documenting the CSI2 and Bridge modules.

Thanks to anyone who can answer any of the above questions!


John

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi John,

The above table 34 and Table 35 are for iMX8MQ, not for iMX8MM. The iMX8MM MIPI CSI2 should reference to iMX7D's. 

Table for HSSETTLE[7:0] and CLKSETTLECTL[1:0].

6,141 Views
tom_perman
Contributor III

Hi,

I am also developing a product using the iMX8MM SoC, and hence this is very useful information. Can I request that this table is added to the official IMX8MM documentation (e.g Reference Manual)? I think this would reduce the amount of confusion regarding correct configuration. 

Thanks,

Tom 

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john_obendorfer
Contributor II

Thank you for the clarification!

The "MIPI serial clock frequency" in the first column: is that a) the MIPI_CSI_CLK_ROOT frequency, or b) the MIPI clock lane frequency?  On our board, the device tree parameter "clock-frequency"  is set to 333MHz, while the MIPI clock lane is running at 1.188GHz.  I think the value I want to use in the table lookup is 333MHz, but thought should ask ... 

Thanks & Regards,

John

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi John,

It should be the MIPI clock lane frequency * 2. So it follows the external MIPI CSI2 input signal. You don't need change the CPU internal MIPI_CSI_CLK_ROOT.

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john_obendorfer
Contributor II

Thank you!

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robrechtbisscho
Contributor II

Thank you for your answer. But it is still not clear to me however. In your table there is only the value 0 for CLKSETTLECTL while in the device tree value 2 is used.

I also assume that de MIPI clock in the table you provide is DDR? So when i measure a MIPI clock of 112MHz using a scope i would have to actually use 224MHz in the table?

I can not seem to map the used values in the device tree to the values in the table.

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qiang_li-mpu_se
NXP Employee
NXP Employee

The table is for DDR mode, so your setting 224MHz is OK.

The CLKSETTLECTL setting is not important, the old BSP hasn't set it, just used the default register value 0.

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laurent_pinchar
Contributor I

I'm afraid this doesn't seem correct. Using the imx_5.4.70_2.3.0 kernel branch unmodified, with csis-clk-settle set to 2, images can be captured. When setting csis-clk-settle to 0, no frame is produced by the device. I've started a thread to focus on this particular issue in https://community.nxp.com/t5/i-MX-Processors/How-to-compute-S-CLKSETTLECTL-value-for-MIPI-CSI-2-rece.... Knowing how to calculate the S_CLKSETTLECTL value is especially important when bringing up a different camera sensor.

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robrechtbisscho
Contributor II

But then I still don't understand why value 13 is used for the OV5640 driver on the SABRE board. When I measure the mipi clock with a scope I get the 112MHz (224MHz DDR), while according to your table the value 13 corresponds to 590~630MHz. How is it possible that this works for the OV5640?

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