Enable CLKOUT1 in Imx8mp eval board

[araja]

Hi,

I am trying to enable 24Mhz clock output from i.MX8mp by following the ov5640 sensor in source and dts files.

I need a 24Mhz clock as a source for MIPI to CSI-2 bridge driver from Toshiba.

After making all changes I am not able to capture the clock signals in the test point of the CLKOUT1.

Currently, I do not have the bridge driver IC attached to the processor but wanted to check all the interface signals are working fine, Like clock, reset, and power pins.

My dts, 

tc9591x: tc9591x_mipi@1c {
        compatible = "toshiba,tc9591x";
        reg = <0x1c>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_csi_rst>;
        clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
        clock-names = "xclk";
        assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
        assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
        assigned-clock-rates = <24000000>;
        csi_id = <0>;
        reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
        mclk = <24000000>;
        mclk_source = <0>;
        mipi_csi;
        status = "okay";

        port {
            tc9591_mipi_1_ep: endpoint {
                remote-endpoint = <&mipi_csi1_ep>;
                link-frequencies = /bits/ 64 <500000000>;
                data-lanes = <1 2 3 4>;
                clock-lanes = <0>;
            };
        };
    };

  pinctrl_csi_rst: csi_rst_grp {
        fsl,pins = <
            MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00    0x106
>;
    };

&mipi_csi_1 {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";

    port@1 {
        reg = <1>;
        mipi_csi1_ep: endpoint {
            remote-endpoint = <&tc9591_mipi_1_ep>;
            link-frequencies = /bits/ 64 <750000000>;
            data-lanes = <4>;
            clock-lanes = <0>;
            csis-hs-settle = <13>;
            csis-clk-settle = <2>;
            csis-wclk;
        };
    };
};

Also made changes in clk-imx8mp.c as suggested by the forum.

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index aa80334196ff..6e6e9b871f54 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -1018,12 +1018,19 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
                          hws[IMX8MP_ARM_PLL_OUT]->clk,
                          hws[IMX8MP_CLK_A53_DIV]->clk);

+    clk_set_parent(hws[IMX8MP_CLK_A53_SRC]->clk, hws[IMX8MP_SYS_PLL1_800M]->clk);
+    clk_set_parent(hws[IMX8MP_CLK_A53_CORE]->clk, hws[IMX8MP_ARM_PLL_OUT]->clk);
+
     imx_check_clk_hws(hws, IMX8MP_CLK_END);

     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);

     imx_clk_init_on(np, hws);
-    
+
+    //enable clkout1 to 24Mhz
+    clk_set_parent(hws[IMX8MP_CLK_IPP_DO_CLKO1]->clk, hws[IMX8MP_CLK_24M]->clk);
+        clk_prepare_enable(hws[IMX8MP_CLK_IPP_DO_CLKO1]->clk);
+
     imx_register_uart_clocks(4);

     return 0;

After doing all the changes still i am not getting the clock signals from the clkout1 pin.

Please guide me to know what I am missing here. 

Some assumptions,

1. If the Bridge driver is not present then the kernel driver will fail on probing and this lead to stopping the clock. In this case, the clock should be present at the initial stage of the power cycle before the driver finds the driver IC is missing. ?.

2. is there a way to enable the clock alone for testing by changing the dts file and source code?

3. Can the clock signals be captured by an oscilloscope from the CLKOUT1 pin without any load?

Correct me if my understanding is wrong.

Thank you very much.

[araja]

Hi,

Any updates,

The control of CLKOUT1 option is not available in kernel 5.15.32 then I have to re-design the hardware so that the clockout1 can be taken from the mux pin GPIO01_14  MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1.  

Please let me know.

[araja · Accepted solution]

This patch has solved the problem for kernel version 5.15.32.

/drivers/clk/imx/clk-imx8mp.c

static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
						  "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
						  "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
						  "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};

 
hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4,
						      imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4);
hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8);
hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4,
						      imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);

clk_set_parent(hws[IMX8MP_CLK_CLKOUT1]->clk, hws[IMX8MP_CLK_24M]->clk);
clk_prepare_enable(hws[IMX8MP_CLK_CLKOUT1]->clk);


/include/dt-bindings/clock/imx8mp-clock.h
 
#define IMX8MP_CLK_CLKOUT1_SEL			324
#define IMX8MP_CLK_CLKOUT1_DIV			325
#define IMX8MP_CLK_CLKOUT1			326
#define IMX8MP_CLK_CLKOUT2_SEL			327
#define IMX8MP_CLK_CLKOUT2_DIV			328
#define IMX8MP_CLK_CLKOUT2			329

#define IMX8MP_CLK_END				337
  

[araja]

Also tried following this solution with no luck 

https://community.nxp.com/t5/i-MX-Processors/enable-CLKO2-for-24MHz-output-clock-on-iMX8MN/m-p/12816...

[araja]

Initially, I tried as you suggested.

Later I understood the clks[] and IMX8MP_CLK_CLKO1 definitions are not available in my version of the source code.

So under drivers/clk/imx/clk-imx8mp.c 

I added the below lines which I assume it is the same as you suggested.

clk_set_parent(hws[IMX8MP_CLK_IPP_DO_CLKO1]->clk, hws[IMX8MP_CLK_24M]->clk);
clk_prepare_enable(hws[IMX8MP_CLK_IPP_DO_CLKO1]->clk);

Please advise what I am missing.

[joanxie]

what bsp version do you use? and what clock do you get after you change the source code? pls share more detailed information

[araja]

what bsp version do you use? 5.15.32

what clock do you get after you change the source code? No clock captured by oscilloscope 

pls share more detailed information: 

I need a 24Mhz clock running on CLKOUT1 which is pin number K29 in i.MX8mp processor.

This clock will be the source for CSI-2 Parallel to MIPI bridge IC. 

If you see my above post for the DTS file I have configured the Bridge IC under the i2c interface and under that node, I have clock configuration for CLKOUT1.

Also as added two lines in clk-imx8mp.c to enable the parent and clock. 

with all those changes I could not capture the clock in the test point of the SOM.

Note: At present, I don't have the Bridge IC attached to the eval board, I just wanted to see the clock running with 24Mhz on CLKOUT1 to move forward with my driver development. 

Please let me know if you need any details.

Thank You 

[joanxie]

how about adding these in the clock driver?

clk_set_parent(clks[IMX8MP_CLK_CLKO1], clks[IMX8MP_CLK_24M]);
clk_prepare_enable(clks[IMX8MP_CLK_CLKO1]);