EIM interface

[saida]

hi

I.mx6 community

can any one help me in this regard

i have connected sram on eim bus and eim configured as half for NOR flash(64mb) and half for SRAM(32mb) and FPGA(32mb) for dualite

Register settings what i have done is

GPR1=0x4840001b

cs1 registers:(0x021b8018)

GCR1=0X00610081

GCR2=0X00001002

RCR1=0X1C022000

RCR2=0X0

WCR1=0X1C092480

WCR2=0X0

IOMUX (its default to lower half data bus)

so when i try to write data to sram through ds5 debugger 1 and 3 nibble is not changing only 0 and 2 modifying accordingly

what could be the problem is there any register to set

and NOR FLASH is also connected on lower half databus

thanks and regards

saida

[igorpadykov]

Hi saida

can you confirm that iomux CSI0_x signals are set to ALT1:

for example EIM_DATA00 --> CSI0_DATA_EN (ALT1),

EIM_DATA01 --> CSI0_VSYNC (ALT1)   .. ?

For GCR1=0X00610081 (DSZ=1), EIM data is allocated

on lower half bus: EIM_DATA0-15, these signals are muxed on

CSI0_DATx pads, which by default (out of reset) are configured as

GPIOs.

Best regards

igor

[saida]

this is continuation from my last reply

even default to lower half i am making them lower half through arm ds5 also

one thing i need clarification, i am using Cypress SRAM, in this case is it Sufficient to Change CONFIG_SYS_TEXT_BASE to 0x0c000000 (where my SRAM located on CS1) and ( instead of  0x17800000 ddr address). i am interfacing SRAM in 32bit mode, any how NORFLASH boots from LowerHalf and PADS are done accordingly and for higher half i want to initialize IOMUX in u-boot, where before u-boot relocates to RAM. can you tell me where exaclty i need to add my assembly code in u-boot before relocation.

thanks and regards

saida

[igorpadykov]

iomux configuration can be done in uboot flash_header.S

~igor

[saida]

have you seen my last post regarding SRAM to load u-boot

thanks and regards

saida

[igorpadykov]

if this problem is different from eim, then it should be

discussed in new thread.

Best regards

igor

[saida]

hi

after spending time on SRAM i am out of trouble now

i solved the problem

thank you

[saida]

thank you for your reply

i makeing CSIO_DATx pads are default to EIM_DATA lower half from EIM_BOOT that is NOR flash 16bit boot (A+LH) from page refmanual(DLRM)398,8.5.1 (10 option)