EIM Bus Timing Parameters

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EIM Bus Timing Parameters

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tom1
Contributor II

Hi,

     In the i.MX6 Dual/Quad Applications Processor for Industrial Products data sheet, table 37 gives the EIM bus timing parameters.  They appear to not be related to the timing waveform diagrams: figure 12, 13, etc.

     For example, the WE4 parameter is described as "Clock rise to address valid" and is a maximum value.  On Figure 12, the WE4 parameter is shown from EIM_ADDRxx to EIM_BCLK which does not make sense.  A maximum value from the address to BCLK does not match the description(or cause and effect)

     I would assume the WE4 parameter is the clock to output time from EIM Clock(not BCLK) to the EIM_ADDRxx output.  That would also make sense if the value is a maximum(i.e. causing the minimum amount of setup time at the target).

     Does anyone have the correct timing waveform diagrams that match the descriptions in table 37?

Thanks for your time,

Tom

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi, Tom

there are no other timing waveform diagrams except provided in datsheet.

Also let me give some comments below:

>On Figure 12, the WE4 parameter is shown from EIM_ADDRxx to EIM_BCLK

>which does not make sense.

It does make sense because table 37 gives WE4 parameter with negative value,

that is "WE4 parameter is the clock to output time from BCLK to the EIM_ADDRxx output"

as you correctly assumed.

Figures 12, 13 are synchronous waveforms that is all EIM timings are referenced from BCLK,

as correctly depicted on these pictures.

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tom1
Contributor II

OK.  I see what you are saying.

Thanks,

Tom

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