i.MX6 LVDS AC spec.

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i.MX6 LVDS AC spec.

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satoshishimoda
Senior Contributor I

Hi community,

I have some questions about i.MX6 LVDS spec.

[Q1]
Please see chapter 4.7.3 in IMX6DQCEC Rev.2.3.
There is "Operating Frequency" in Table 32, but there is not it in Figure 6.
So I want to confirm what is it.
I think it is a LVDS clock (LVDSx_CLK_x), is this correct?

[Q2]
Are there spec of "high levelo width" and "low level width" of LVDS clock?

[Q3]
There is no AC spec between LVDS clock and LVDS data.
Do you have it?

[Q4]
Do you have a spec about jitter of LVDS output?


Best Regards,
Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

>[Q1]

Table 32 and Figure 6 describe all LVDS pads, this applicable to

LVDS clock (LVDSx_CLK_x) too.

[Q2],[Q3],[Q4]>

LVDS specifications use different timing concepts, than

"AC spec between LVDS clock and LVDS data" and

"high level width" and "low level width" of LVDS clock.

In particular EIA_644A standard [p.4] only requires that:

"The recommended signal transition time (tr, or tf) at the load should

not exceed 0.5 of the unit interval to preserve signal quality."

For LVDS timing requirements "eye pattern" analysis is used and based on

"eye pattern" test one can calculate allowable jitter, depending

on cable and its length. Please refer to app notes below and

other LVDS related app notes from other vendors.

National AN1088

https://archive.org/details/bitsavers_nationalap_130763

TI AN1059

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=snla050&fileType=pdf

Maxim AN1856

http://www.maximintegrated.com/app-notes/index.mvp/id/1856

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igorpadykov
NXP TechSupport
NXP TechSupport

>[Q1]

Table 32 and Figure 6 describe all LVDS pads, this applicable to

LVDS clock (LVDSx_CLK_x) too.

[Q2],[Q3],[Q4]>

LVDS specifications use different timing concepts, than

"AC spec between LVDS clock and LVDS data" and

"high level width" and "low level width" of LVDS clock.

In particular EIA_644A standard [p.4] only requires that:

"The recommended signal transition time (tr, or tf) at the load should

not exceed 0.5 of the unit interval to preserve signal quality."

For LVDS timing requirements "eye pattern" analysis is used and based on

"eye pattern" test one can calculate allowable jitter, depending

on cable and its length. Please refer to app notes below and

other LVDS related app notes from other vendors.

National AN1088

https://archive.org/details/bitsavers_nationalap_130763

TI AN1059

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=snla050&fileType=pdf

Maxim AN1856

http://www.maximintegrated.com/app-notes/index.mvp/id/1856

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