I have been working with the ECSPI module exported on the J1003 pins of the i.MX 8 Mini evaluation kit (imx8mmevk).
I have edited the DeviceTree to include a proper node under the ecspi node, written a driver for it and it communicates fine.
I am using a single SPI message with a single transfer, sent by spi_async(). I have noticed that for transfer lengths <32B, the driver spi-imx.c uses PIO implementation and transfers the bytes with CS = low, as it should (except that for len=30, the last two bytes are sent somewhat later, and CS toggles in between).
However, my question is about DMA transfer, which is used for len>=32. In this mode, the CS signal toggles after each word. How can this behavior be suppressed? Alternatively, how can the PIO mode be made to transfer all the bytes at the same time, without toggling CS?
已解决! 转到解答。
dnortmeyer@de.pepperl-fuchs.com
I have finally solved this issue by using a GPIO pin for Slave Select instead of the SS0 signal. I was propmted to do so by the file include/linux/platform_data/spi-imx.h in the Linux kernel sources, which literally says:
Normally you want to use gpio based chip selects as the CSPI module tries to be intelligent about when to assert the chipselect: The CSPI module deasserts the chipselect once it runs out of input data.
So I have done the following:
Now the SPI works like a charm and the chipselect is low across the whole SPI transfer.
Note:
- pin 7 is GPIO5_IO8
- pin 8 is GPIO5_IO7
- pin 10 is GPIO5_IO6
- pin 11 is GPIO5_IO9
- see include/dt-bindings/pinctrl/pins-imx8mm.h in the Linux kernel source for possible configurations
Hope this helps.
dnortmeyer@de.pepperl-fuchs.com
I have finally solved this issue by using a GPIO pin for Slave Select instead of the SS0 signal. I was propmted to do so by the file include/linux/platform_data/spi-imx.h in the Linux kernel sources, which literally says:
Normally you want to use gpio based chip selects as the CSPI module tries to be intelligent about when to assert the chipselect: The CSPI module deasserts the chipselect once it runs out of input data.
So I have done the following:
Now the SPI works like a charm and the chipselect is low across the whole SPI transfer.
Note:
- pin 7 is GPIO5_IO8
- pin 8 is GPIO5_IO7
- pin 10 is GPIO5_IO6
- pin 11 is GPIO5_IO9
- see include/dt-bindings/pinctrl/pins-imx8mm.h in the Linux kernel source for possible configurations
Hope this helps.
dnortmeyer@de.pepperl-fuchs.com
Hello,
I hope, the following clarifies the issue.
Control SPI SS_CTL for single burst operation.
Regards,
Yuri.