ECSPI chipselect toggle after each word with DMA

[jan_remes]

I have been working with the ECSPI module exported on the J1003 pins of the i.MX 8 Mini evaluation kit (imx8mmevk).

I have edited the DeviceTree to include a proper node under the ecspi node, written a driver for it and it communicates fine.

I am using a single SPI message with a single transfer, sent by spi_async(). I have noticed that for transfer lengths <32B, the driver spi-imx.c uses PIO implementation and transfers the bytes with CS = low, as it should (except that for len=30, the last two bytes are sent somewhat later, and CS toggles in between).

However, my question is about DMA transfer, which is used for len>=32. In this mode, the CS signal toggles after each word. How can this behavior be suppressed? Alternatively, how can the PIO mode be made to transfer all the bytes at the same time, without toggling CS?

[jan_remes · Accepted solution]

dnortmeyer@de.pepperl-fuchs.com‌

YuriMuhin_ng‌

I have finally solved this issue by using a GPIO pin for Slave Select instead of the SS0 signal. I was propmted to do so by the file include/linux/platform_data/spi-imx.h in the Linux kernel sources, which literally says:

Normally you want to use gpio based chip selects as the CSPI module tries to be intelligent about when to assert the chipselect: The CSPI module deasserts the chipselect once it runs out of input data.

So I have done the following:

1. In the DeviceTree, I have configured the ECSPI to have two CS lines with:
   &ecspi2 {
       ...
       cs-gpios = <0>, <&gpio5 8 GPIO_ACTIVE_LOW>;
       ...
   };
   
   AFAIK, this means that child node with reg = <0>; is selected by ECSPI's integrated SS0 signal and child node with reg = <1>; is selected by activating (pulling low) the GPIO5_IO8.
   
   
2. In the DeviceTree, I have configured the pins 7,8,10,11 (on the J1003 header of the evaluation board) to work as GPIO pins thus:
   
   /* Disable the UART3 device that was originally using those pins and delete its pin control settings */
   &uart3 {
           /delete-property/ pinctrl-names;
           /delete-property/ pinctrl-0;
           status = "disabled";
   };
   
   &iomuxc {
           imx8mmevk {
                   /delete-node/ uart3grp;
           };
   };
   
   /* Setup the pins to be MUXed to GPIO controller */
   &iomuxc {
           imx8mm-evk {
                   pinctrl_adc: adcgrp {
                           fsl,pins = <
                                   MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6      0x140
                                   MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7      0x140
                                   MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x140
                                   MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8      0x140
                           >;
                   };
           };
   };
   
3. In my SPI device DeviceTree description, I used reg = <1>;
   
   
4. I have physically connected the ChipSelect wire of my SPI device to J1003 pin 7 (labeled UART3_CTS).

Now the SPI works like a charm and the chipselect is low across the whole SPI transfer.

Note:

- pin 7 is GPIO5_IO8

- pin 8 is GPIO5_IO7

- pin 10 is GPIO5_IO6

- pin 11 is GPIO5_IO9

- see include/dt-bindings/pinctrl/pins-imx8mm.h in the Linux kernel source for possible configurations

Hope this helps.

[Yuri]

jan.remes@invasys.com 

dnortmeyer@de.pepperl-fuchs.com 

Hello,

   I hope, the following clarifies the issue.

Control SPI SS_CTL for single burst operation. 

Regards,

Yuri.

[Yuri]

jan.remes@invasys.com 

Hello,

   I've sent some comments directly to You.

Regards,

Yuri

[dnortmeyer]

Hi Yuri,

I have the same problem regarding the chip select toggling while making DMA transfers. Could you please send me the comments too?

Kind regards,

Dominik