Dual channel memory access for DDRL3 SDRAM

[erlend_eriksen]

I want to configure my imx6q so that the VPU and the A9 cores use two separate channels / AXI buses. However, I'm locked to DDRL3 memory, and  in the documentation on the MMDC ( i.MX 6DQ Reference Manual (IMX6DQRM R2, Part 2) ) it seems to say that dual channel support is limited to LPDDR2.

So does this mean that I have no way of separating the memory access of VPU and CPU without switching to LPDDR2?

Are there any plans to enable dual channel memory access for DDRL3 in the future?

LPDDR2LPDDR2

[igorpadykov]

Hi Erlend

>So does this mean that I have no way of separating the memory access of

>VPU and CPU without switching to LPDDR2?

right.

>Are there any plans to enable dual channel memory access for DDRL3 in the future?

no plans, sorry.

Best regards
igor
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