This is a copy of the currently posted i.MX 6DQ reference manual, revision 2, published Jun 2014. This is part 2 of 2, and includes chapters 44-71, Appendix A and Appendix B. Go here for part 1: i.MX 6DQ Reference Manual (IMX6DQRM R2, Part 1)
This document is to be used to enter community comments. Please feel free to add inline comments in this reference manual. You can point out where more information is needed or where existing information is incorrect. You can also enter information in your comment that expands on existing information in the document, based on your experience with the device. If you are pointing out that more information is needed in a paragraph or a section, please be very specific, not “needs more information”. Your comments in this manual may help other members and will drive improvements in this and future documentation.
Note: The doc viewer does not support going directly to a specified page. Instead of manually paging through one page at a time, you can do a search on a string on a page such as "types of resets", or you can go to chapter links listed in the inline comments. To do this, page down to the comments below the doc view, select "Inline Comments", sort the comments by "page", and then select the chapter you want to view. You may find it easier to use this manual by downloading and viewing it in your local Adobe Reader. Then when you have a comment/question to add to this review copy, navigate to the chapter as described above and then do a search on the text for which you want to add a comment. This will take you to that page the quickest.
Hit the "Inline Comments" link above to see links to each chapter.
Chapter Order:
Chapter 1: Introduction
Chapter 2: Memory Maps
Chapter 3: Interrupts and DMA Events
Chapter 4: External Signals and Pin Multiplexing
Chapter 5: Fusemap
Chapter 6: External Memory Controllers
Chapter 7: System Debug
Chapter 8: System Boot
Chapter 9: Multimedia
Chapter 10: Clock and Power Management
Chapter 11: System Security
Chapter 12: ARM Cortex A9 MPCore Platform (ARM)
Chapter 13: AHB to IP Bridge (AIPSTZ)
Chapter 14: AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
Chapter 15: Asynchronous Sample Rate Converter (ASRC)
Chapter 16: Digital Audio Multiplexer (AUDMUX)
Chapter 17: 40-BIT Correcting ECC Accelerator (BCH)
Chapter 18: Clock Controller Module (CCM)
Chapter 19: MIPI CSI to IPU Gasket (CSI2IPU)
Chapter 20: Display Content Integrity Checker (DCIC)
Chapter 21: Enhanced Configurable SPI (ECSPI)
Chapter 22: External Interface Module (EIM)
Chapter 23: 10/100/1000-Mbps Ethernet MAC (ENET)
Chapter 24: Enhanced Periodic Interrupt Timer (EPIT)
Chapter 25: Enhanced Serial Audio Interface (ESAI)
Chapter 26: Flexible Controller Area Network (FLEXCAN)
Chapter 27: General Power Controller (GPC)
Chapter 28: General Purpose Input/Output (GPIO)
Chapter 29: General Purpose Media Interface (GPMI)
Chapter 30: General Purpose Timer (GPT)
Chapter 31: 2D Graphics Processing Unit (GPU2D)
Chapter 32: 3D Graphics Processing Unit (GPU3D)
Chapter 33: HDMI Transmitter (HDMI)
Chapter 34: HDMI 3D Tx PHY (HDMI_PHY)
Chapter 35: I2C Controller (I2C)
Chapter 36: IOMUX Controller (IOMUXC)
Chapter 37: Image Processing Unit (IPU)
Chapter 38: Keypad Port (KPP)
Chapter 39: LVDS Display Bridge (LDB)
Chapter 40: MIPI - Camera Serial Interface Host Controller (MIPI_CSI)
Chapter 41: MIPI DSI Host Controller (MIPI_DSI)
Chapter 42: MIPI HSI Host Controller (MIPI_HSI)
Chapter 43: MediaLB (MLB)
Chapter 44: Multi Mode DDR Controller (MMDC)
Chapter 45: Network Interconnect Bus System (NIC-301)
Chapter 46: On-Chip OTP Controller (OCOTP_CTRL)
Chapter 47: On-Chip RAM Memory Controller (OCRAM)
Chapter 48: PCI Express (PCIe)
Chapter 49: PCI Express PHY (PCIe_PHY)
Chapter 50: Power Management Unit (PMU)
Chapter 51: Pulse Width Modulation (PWM)
Chapter 52: ROM Controller with Patch (ROMC)
Chapter 53: Serial Advanced Technology Attachment Controller (SATA)
Chapter 54: Serial Advanced Technology Attachment PHY (SATA PHY)
Chapter 55: Smart Direct Memory Access Controller (SDMA)
Chapter 56: System JTAG Controller (SJC)
Chapter 57: Secure Non-Volatile Storage (SNVS)
Chapter 58: Shared Peripheral Bus Arbiter (SPBA)
Chapter 59: Sony/Philips Digital Interface (SPDIF)
Chapter 60: System Reset Controller (SRC)
Chapter 61: Synchronous Serial Interface (SSI)
Chapter 62: Temperature Monitor (TEMPMON)
Chapter 63: TrustZone Address Space Controller (TZASC)
Chapter 64: Universal Asynchronous Receiver/Transmitter (UART)
Chapter 65: Universal Serial Bus Controller (USB)
Chapter 66: Universal Serial Bus 2.0 Integrated PHY (USB-PHY)
Chapter 67: Ultra Secured Digital Host Controller (uSDHC)
Chapter 68: Video Data Order Adapter (VDOA)
Chapter 69: Video Processing Unit (VPU)
Chapter 70: Watchdog Timer (WDOG)
Chapter 71: Crystal Oscillator (XTALOSC)
Title Order:
10/100/1000-Mbps Ethernet MAC (ENET): Chapter 23
2D Graphics Processing Unit (GPU2D): Chapter 31
3D Graphics Processing Unit (GPU3D): Chapter 32
40-BIT Correcting ECC Accelerator (BCH): Chapter 17
AHB to IP Bridge (AIPSTZ): Chapter 13
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA): Chapter 14
ARM Cortex A9 MPCore Platform (ARM): Chapter 12
Asynchronous Sample Rate Converter (ASRC): Chapter 15
Clock and Power Management: Chapter 10
Clock Controller Module (CCM): Chapter 18
Crystal Oscillator (XTALOSC): Chapter 71
Digital Audio Multiplexer (AUDMUX): Chapter 16
Display Content Integrity Checker (DCIC): Chapter 20
Enhanced Configurable SPI (ECSPI): Chapter 21
Enhanced Periodic Interrupt Timer (EPIT): Chapter 24
Enhanced Serial Audio Interface (ESAI): Chapter 25
External Interface Module (EIM): Chapter 22
External Memory Controllers: Chapter 6
External Signals and Pin Multiplexing: Chapter 4
Flexible Controller Area Network (FLEXCAN): Chapter 26
Fusemap: Chapter 5
General Power Controller (GPC): Chapter 27
General Purpose Input/Output (GPIO): Chapter 28
General Purpose Media Interface (GPMI): Chapter 29
General Purpose Timer (GPT): Chapter 30
HDMI 3D Tx PHY (HDMI_PHY): Chapter 34
HDMI Transmitter (HDMI): Chapter 33
I2C Controller (I2C): Chapter 35
Image Processing Unit (IPU): Chapter 37
Interrupts and DMA Events: Chapter 3
Introduction: Chapter 1
IOMUX Controller (IOMUXC): Chapter 36
Keypad Port (KPP): Chapter 38
LVDS Display Bridge (LDB): Chapter 39
MediaLB (MLB): Chapter 43
Memory Maps: Chapter 2
MIPI - Camera Serial Interface Host Controller (MIPI_CSI): Chapter 40
MIPI CSI to IPU Gasket (CSI2IPU): Chapter 19
MIPI DSI Host Controller (MIPI_DSI): Chapter 41
MIPI HSI Host Controller (MIPI_HSI): Chapter 42
Multi Mode DDR Controller (MMDC): Chapter 44
Multimedia: Chapter 9
Network Interconnect Bus System (NIC-301): Chapter 45
On-Chip OTP Controller (OCOTP_CTRL): Chapter 46
On-Chip RAM Memory Controller (OCRAM): Chapter 47
PCI Express (PCIe): Chapter 48
PCI Express PHY (PCIe_PHY): Chapter 49
Power Management Unit (PMU): Chapter 50
Pulse Width Modulation (PWM): Chapter 51
ROM Controller with Patch (ROMC): Chapter 52
Secure Non-Volatile Storage (SNVS): Chapter 57
Serial Advanced Technology Attachment Controller (SATA): Chapter 53
Serial Advanced Technology Attachment PHY (SATA PHY): Chapter 54
Shared Peripheral Bus Arbiter (SPBA): Chapter 58
Smart Direct Memory Access Controller (SDMA): Chapter 55
Sony/Philips Digital Interface (SPDIF): Chapter 59
Synchronous Serial Interface (SSI): Chapter 61
System Boot: Chapter 8
System Debug: Chapter 7
System JTAG Controller (SJC): Chapter 56
System Reset Controller (SRC): Chapter 60
System Security: Chapter 11
Temperature Monitor (TEMPMON): Chapter 62
TrustZone Address Space Controller (TZASC): Chapter 63
Ultra Secured Digital Host Controller (uSDHC): Chapter 67
Universal Asynchronous Receiver/Transmitter (UART): Chapter 64
Universal Serial Bus 2.0 Integrated PHY (USB-PHY): Chapter 66
Universal Serial Bus Controller (USB): Chapter 65
Video Data Order Adapter (VDOA): Chapter 68
Video Processing Unit (VPU): Chapter 69
Watchdog Timer (WDOG): Chapter 70