We don't document the registers of the DDRC PHY, but for this specific feature (in fact this is a requirement of JESD209-4B) you find at least an indication that it is enabled:
bernhardfink_0-1726227597651.png
In the lpddr4x_timing.c file you can't identify this bit without having a detailed description of the registers, but as Pengyong wrote, it is enabled by default.
Regards,
Bernhard.