Display interface clock

[carmilili]

Hello,

I meet a trouble probem with the display clock.

The CPU is IMX6Q.I use the DISP0 to sent YUV to FPGA.The driver is "mxc_lcdif.c".

The image is not normal.You can look the image below .

Now I find  the reason is the DISP0 pix clock.

When the pix clock pin do not connect to the FPGA.It will be 3.3vpp when output all kinds of frequency  clock.

But when I connect IMX6Q via a 33R resistor to FPGA, the VPP of clock is the higher frequency the more low,and the clock offset from the GND.

Dose someone can help me to solve it?

Thank you!

image

schematic diagram

33MHz

75MHz

[igorpadykov]

Hi Carmili

there is one good and simple solution: use shorter LCD cable and decrease 33R resistor value

(this will decrease clock offset from the GND). Other solutions are not so simple and

reliable and require understanding physics of termination high speed lines. You

can look at links below for them.

sect.2.2.6 "Termination Schemes" AN2536 High Speed Layout Design Guidelines

http://www.freescale.com/files/32bit/doc/app_note/AN2536.pdf

http://www.analog.com/library/analogdialogue/archives/44-01/clock_termination.html

http://www.marvintest.com/KnowledgeBase/KBArticle.aspx?ID=196

Best regards

chip

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