Hello !
Please look at my comments below.
1.
> What is a function of the box that is between ④ and ⑤ ?
This is a latch register.
2.
> In my understandig, the clock that is shown in ① in Figure 67-20 is ref_clk.
> Is it correct ?
The clock ① is a derivative of “Card_clk”, mentioned on both figures 67-20 and 67-2.
2.1.
> Does it change their name to "ipp_card_clk_in" ?
“ipp_card_clk_in” is internal signal - from “card_clk_pad” (SDx_CLK of SD interface).
3.
> What is different between disabled and bypassed ?
According to section 67.5.3.2.4 [DLL (Delay Line) in Read Path] of the RM,
“The reasons why the DLL is needed for uSDHC are 1.) the path of read data traveling
from card to host varies. 2.) in SD/MMC DDR mode the minimum input setup and hold
time are both at 2.5 ns. The data sampling window is so small that the delay of loopback
clock needs to be accurate and consistent regardless of PVT”.
The DLL is needed for high frequency cases, in particular for the DDR mode.
4.
> Is the read path same that is shown in Figure 67-20 when user disabled or bypassed the DLL ?
Basically – yes. But “ipp_card_clk_in_dll” “and ipp_card_clk_in” are the same : the “delay line”
is skipped.
Have a great day,
Yuri
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