Hi,
I'm working with the i.MX8M Plus platform and using the `imx-vpu-hantro` package for hardware-accelerated video decoding. While testing the HEVC decoder using the provided testbench (`hevcdec` from `decoder_sw`), I'm encountering a decoder initialization failure.
Here are the details:
- Platform: i.MX8MP
- Kernel: 6.6.52
- Package: imx-vpu-hantro
- Testbench: hevcdec
- Input stream: Animation.h265 (valid HEVC stream)
- CMA: Enabled (`CmaTotal: 983040 kB`, `CmaFree: 945624 kB`)
- Driver: `hantro_vpu` found
- DTS: VPU node status is `"okay"`
**Console Output:**
./hevcdec Animation.h265
Hevc SW build: 196609 - HW build: 67323088
Decoder Macro Block Error Concealment 0
Decoder RLC 0
Decoder Clock Gating 1
Decoder Clock Gating Runtime0
Decoder Data Discard 0
Decoder Latency Compensation 0
Decoder Output Picture Endian 1
Decoder Bus Burst Length 16
Decoder Asic Service Priority 0
Decoder Output Format 0
TB Packet by Packet 0
TB Nal Unit Stream 0
TB Seed Rnd 1
TB Stream Truncate 0
TB Stream Header Corrupt 0
TB Stream Bit Swap 0; odds 0
TB Stream Packet Loss 0; odds 0
DWL Before:0
DWL After:0
DECODER INITIALIZATION FAILED
Decoding ended, flush the DPB
Releasing 0 external frame buffers
Output file: out.yuv
OUTPUT_SIZE 0
SW_PERFORMANCE 0.00001
DECODING DONE
It appears the DWL layer is failing to initialize, possibly due to missing hardware bindings or driver registration. I’ve verified that CMA is available, but the Hantro VPU driver may not be loaded or built correctly.
Could you please advise on:
- Required kernel config options for Hantro HEVC decoding
- Device tree bindings for enabling the VPU
- Whether `hevcdec` requires `/dev/videoX` nodes or specific firmware
- Any known issues with `imx-vpu-hantro` on recent kernels
Any guidance would be greatly appreciated.
Thank you.