DRAM Trim Controls

[RobertC]

Hello,

Document Number: IMX6DQRM, Rev. 5, 06/2018.  

In section 44.11.9, it talks about a 2-bit control field to add a fixed delay to SDCLK or SDQS signals.  Is it true?  I could not find any information on the reference manual.  The referenced registers do not contain such control field.  The corresponding bit fields in IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 (IOMUX_SW_PAD_CTL_PAD_ADDR00) are for something else.  Does that feature exist to a fixed delay to SDCLK?

Thanks,
Rob

[Yuri · Accepted solution]

@RobertC 
Hello,

   according to section 8 (External memory) of i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus  Comparison the trim control was introduced for i.MX 6DualPlus/6QuadPlus
(i.MX 6Dual/6Quad  does not support such feature):

  The i.MX 6DualPlus/6QuadPlus will have the same external Memory as i.MX 6Dual/6Quad.
Although the DRAM controller and frequency will remain the same, the overall DRAM utilization is
significantly improved, due to the improvements in the bus fabric and graphics IP.

 
    The DRAM controller has also been enhanced with additional trim controls for the SDCLKx and SDQSx  signals.

    This updated fine tuning control has been copied from the i. MX 6SoloX family of processors, where it
has been successfully verified on actual products.

Regards,
Yuri.