DDR4 training failed in 2400

[shaotang]

Hi !

  I made a board according to the layout of the imx8mm EVK SOM board. After I got it, I tried to download the u-boot firmware, but I got the following serial port printing information:

U-Boot SPL 2018.03 (Nov 16 2021 - 20:11:06 +0800)
power_bd71837_init
DRAM PHY training for 2400MTS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training FAILED
DRAM PHY training for 400MTS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training PASS
DRAM PHY training for 100MTS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training PASS
DRAM PHY training for 2400MTS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training FAILED

Then there is nothing left.

By positioning, I found that it was stuck in a memset() function in the board_init_r() function. So how can I solve it?

Should I use mscale_ddr_tool? But the layout is according to the EVK board. I don't know...

Please help me in this case.

Thanks!

[igorpadykov]

Hi

yes, recommended to run ddr test and update image according to i.MX 8M Family DDR Stress Test User Guide

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

Best regards
igor

[shaotang]

I have used v15 script to run the ddr test according to i.MX 8M Family DDR Stress Test User Guide, and this is the log:

Downloading file 'bin\ddr4_train1d_string_v201709.bin' ..Done

Downloading file 'bin\ddr4_train2d_string_v201709.bin' ..Done

Downloading file 'bin\ddr4_imem_1d_v201709.bin' ..Done

Downloading file 'bin\ddr4_dmem_1d_v201709.bin' ..Done

Downloading file 'bin\ddr4_imem_2d_v201709.bin' ..Done

Downloading file 'bin\ddr4_dmem_2d_v201709.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC BD718XX**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.20
Built on Feb 23 2021 13:54:04
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x93d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1200MHz

============================================
DDR configuration
DDR type is DDR4
Data width: 32, bank num: 8
For DDR4, bank num is the total of 2 bank groups and 4 banks per group
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M-mini: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1200Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
PMU: Error: Dbyte 3 lane 0 txDqDly passing region is too small (width = 0)
PMU: ***** Assertion Error - terminating *****
[Result] FAILED

I'm very confused, because I made this board according to the EVK board files, please help me....

Thanks!!!

[igorpadykov]

from log "Dbyte 3 " you can recheck board layout for this part. In particular

Step5. Switch to worksheet tab “BoardDataBusConfig” to check data bus assignment.

MSCALE_DDR_Tool_User_Guide.pdf

Best regards
igor

[shaotang]

Hi igor

 I find that there is no worksheet tab “BoardDataBusConfig” in the MX8M_Mini_DDR4_RPA_v15.xlsx, so how can I check the data bus assignment? 

Best regards

tang

[igorpadykov]

sorry tab “BoardDataBusConfig” is for LPDDR4. Regarding error in step 2, from log:

Data read was :   0x0000000040001890
But pattern was : 0x0000000040000080

one can check layout (probably there are errors) and check signals with oscilloscope

data bits which are different.

Best regards
igor

[shaotang]

Hi!

Today I adjusted the 32-bit ddr4 to 16-bit, (I don’t know if it’s the high 16-bit or the low 16-bit, I didn’t find it in the datasheet)

And I used the ddr-test-tool to test it, it's the result:

Training pass, but the step 2 failed. Please give me some advice. Thank you!

Regards

shaotang

[shaotang]

Hello! Thank for your anwser, I'm very grateful. The last question, The error "Dbyte3" means only one Dbyte is mistake in 32 Dbytes or there may be other mistakes in other 31 Dbytes？ best wishes Thanks for your answer!!