DDR3 data pin swapping - How to configure DDR controller to determine the pins swapping?

[alanlow]

Hi,

We design a custom i.MX6ULL board that connect to a DDR3 DRAM (x16) using data pin swapping.

Host D0 <--> DRAM DQU0

Host D8 <--> DRAM DQL0

The rest of pins are swapped within the byte lane.

1) How to configure the DDR controller so that it will read/write the data content correctly?

[bernhardfink]

• For the byte and pin swapping, as I wrote, no software changes are to be made.
• If your 4Gb SDRAM is a different size than the one in the Murata Yocto project you are referring to, then you need to adapt this in the device tree.
• If you want to change the timings or the impedance settings of the DDR, then use the attached Excel file as a basis

Regards,
Bernhard.

[bernhardfink]

You don't need to do anything in software, just follow the rules ...

• The lowest bit of each byte must be aligned between the i.MX 6ULL and DDR3 chips.
  For example, D0 of i.MX 6ULL to D0 of DDR chip, D8 of i.MX 6ULL to D8 of DDR3 chip.
• Other data lines free to swap within byte lane

... and the DDR controller adapts to your actual implementation.

The Note about the "DDR IC" register is not relevant here.

Regards,
Bernhard.

[alanlow]

Hi Bernhard,

Thanks for your speedy response!

1) We are using SK Hynix DDR3L 4Gb SDRAM. The Linux BSP is from Murata Yocto project for i.MX6ULL-EVK. Need your advice if we need to modify any source code from the kernel-source?

2) Is that any configuration available for us to fine-tune the DDR speed?

Regards

[joanxie]

pls refer to the enclosed guide

[alanlow]

Hi Joanxie,

Thanks!