DDR3 - Swapping data lines + IMX6Q

[stevenshi]

hi Freescale:

our board design is base on SDB board,the OS is Android4.4.2.

my problem is in DDR3 Configration. our HW engineers

relayout the board for DDR3, the freeescale "Hareware

development guide" had said that "Swapping data lines"(please

check attachment_1). i found the SDB board has swap the data

lines in freescale board. but our HW engineers swap more data

lines. I want to konw the "flash_header.S" or other file need to

change in uboot??

how to change the software code to adjust the "If byte lane swapping was done, target DDR IC register read value must be

transposed according to the data line swapping"

the DDR3 is very important for our board, please give me some

suggest, thank you!

our board DDR3 chip is same as SDB. the data line different please check attachment_2/attachment_3/attachment_4/attachment_5

[Yuri]

  No need to change the software code in the case.

Have a great day,
Yuri

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[stevenshi]

hi Yuri Muhin:

    thank you for your reply, can you kindly give me explain about "If byte lane swapping was done, target DDR IC register read value must be transposed according to the data line swapping". in hardware develop guide it seem to need change code. but your reply is not need change code. i am very puzzled. otherwise other file need to modify??

[stevenshi]

hi Yuri Muhin:

       can you kindly give me some explains, thank you!

[Yuri]

   I did not hear about DDR IC using ( at least till now).

Regards,

Yuri.

[stevenshi]

OK, thank you for your support!