DDR3 Signal length in i.MX6Q

[keitanagashima]

Dear Sir or Madam,

Hello.

Refer to Table 3-5. Total signal etch (DDR3) in Hardware Development Guide for i.MX6DQ6SDL, Rev. 1.

There is description of DRAM_SDCLK0 : 2120.044[Mils].

My customer measured the DRAM_SDCLK0 length on i.MX6Q SABRE-AI.

Actualｌy the DRAM_SDCLK0 length looked 1849.483[Mils].

Refer to attached file: "DDR3_SDCLK_Length.xlsx"

[Question]

Should we think including the branch wiring about each signal length?

Or, can we ignore the branch wiring length?

BR,

Keita

[art]

Yes, the trace length within a via should be taken into the account when calculating total trace length. However, only the actual trace length should be taken into the account, not always a total board thickness. For example, if a trace goes from Layer 2 to Layer 6 through a via on 8-layer board, only the distance between Layer 2 and Layer 6 should be taken into the account, not total board thickness.

Have a great day,
Artur

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[keitanagashima]

Hi Artur,

Thank you for your reply.

I'd like to know about branched wire when calculating total trace length.

Refer to attached file.

Should we consider the branched wire to calculate total trace length?

Best Regards,

Keita

[art · Accepted solution]

Hi Keita,

No, you have not to include the length of the wire branches you've shown into the total trace length calculation from the processor to the DDR3 chip.

Best Regards,

Artur

[keitanagashima]

Hi Artur,

Thank you for your reply.

OK. I got it!

BR,

Keita