DDR2 Differential vs Single-Ended...

[mbp]

We have been running into intermittent freezing/rebooting issues on some of our beta systems.  Implementation of the PLL patch has resolved a couple and dramatically improved others.  However an issue remains.  From the prevailing evidence it is most DDR related.

Apparently many are having better luck with single-ended operation.

How many of you are operating cleanly in Differential mode and how many in Single-ended mode?

This unofficial survey should help us all determine best memory architecture.

Our platform is heavily based on the MX51EVK (running Android R9.2) using Micron DDR2 memory (identical or better to the Elpida on the EVK).  If anyone has seen improved operation in single-ended mode and would care to share the modified "flash_header.S" file that would be most appreciated.

Thanks All!

(this discussion is mirrored in the Android Group to access the largest target audience)

[N_Coesel]

I had some issues with the memory as well (DDR2-800 Winbond chips). I didn't try single ended so far. I did notice that the automatic memory delay alignment does not work very well. This probably makes the layout of the memory bus extremely critical.

I've used this tool to test the memory:

http://pyropus.ca/software/memtester/

It is quite handy. If the system doesn't lock-up then it will give you a clue which lane is the problem. The IMX51 does allow to insert additional delay for a specific lane.

[martinhowell]

Just seen this thread.

We have had problems with the memory on our iMX51 design also, first production batch worked fine. The next did not. Our engineering solution was to run the DDR at 160MHz instead of 200.

We tried calibrating the delay lines as per Freescales tool but the results we got were unpredictable.