Custom Resolution 800x480

[chriscmorgan]

I have an 800x480 lcd I am looking to configure for the imx8m to run at 800x480 not 1920x1080 it is defaulting to. I am running u-boot 2019.04 and Linux 4.19.35. I am able to set the resolution to 800x480 if I plug the LCD into my windows laptop.

From looking at similar questions it seems I need to add the resolution to edid_cea_modes either in drm_edid.c or imx-dhp.c then update t28hpc_hdmitc_table.c with a new clock speed as per:
https://community.nxp.com/t5/i-MX-Processors/HDMI-DRM-custom-resolution-and-clock-frequency/m-p/1029...

My question is how do you generate the required clock speed for a 800x480&60Hz hdmi LCD? I found this tool: https://tomverbeure.github.io/video_timings_calculator But not sure which modeline to use if any.

This is the LCD I am testing with: https://core-electronics.com.au/waveshare-5inch-lcd-800x480.html 

Any guidance is appreciated. 

[Rita_Wang]

You need to confirm if the pixel clock is in this table, if not, you need to use the "HDMI - pixel clock calculation"

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-ph...

static const struct hdmi_ctrl imx8mq_ctrl_table[]

[cdoumenc]

Link update with new repository location : https://github.com/nxp-imx/linux-imx/tree/lf-5.10.y/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c

[chriscmorgan]

Thanks for your reply. It does look like I need to use the "HDMI - pixel clock calculation" as my required clock speed is 33900 and its not in hdmi_ctrl imx8mq_ctrl_table.

My 800x480 LCD has this modeline  "Mode 0" 33.90 800 844 932 1056 480 483 489 535 +hsync +vsync"

I am a bit lost on how to use this spreadsheet though to get the values for the hdmi_ctrl imx8mq_ctrl_table. Any help on how to get these values from the above modeline?

Reference Clock Freq
Expected Pixel clock
Generated clock tolerance
pll input divider
pll feedback divider
pixel clock divider
character clock divider

Any advice is really appreciated. 

[Rita_Wang]

You can see the doc I have wrote. Hope can do help for you.

As I will have the Spring Festival holiday and I will back to office on the 7th Feb, Maybe update to you then. Thanks a lot for your kindly understandings.

[Rita_Wang]

Which board are you using?

[chriscmorgan]

Using the SMARC-iMX8M:
http://www.embedian.com/index.php?main_page=product_info&products_id=26

On the EVK-STD-CARRIER-S20 carrier board.

[chriscmorgan]

Ok I was able to query get the correct parameters for the lcd via "cat /sys/class/drm/card0-HDMI-A-1/edid | parse-edid"

Which did have this line which is the resolution I want:

"Modeline "Mode 0" 33.90 800 844 932 1056 480 483 489 535 +hsync +vsync"

But when I try to add this mode via xrandr I am getting this error and screen is going black:

Jan 25 11:04:00 smarcimx8m kernel: [ 4234.219299] [drm] Pixel clock frequency: 33900 KHz, character clock frequency: 33900, color depth is 8-bit.
Jan 25 11:04:00 smarcimx8m kernel: [ 4234.219315] [drm] Pixel clock frequency (33900 KHz) not supported for this color depth (8-bit)
Jan 25 11:04:00 smarcimx8m kernel: [ 4234.219331] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock
Jan 25 11:04:00 smarcimx8m kernel: [ 4234.226009] [drm:imx_hdp_bridge_mode_set] *ERROR* Failed to initialise HDP PHY

So it does seem I need to use this "HDMI - pixel clock calculation" spreadsheet and add a new line to t28hpc_hdmitx_table.c.

The challenge I am having is what I need to add the spreadsheet for the input variables:

• Reference Clock Freq
• Expected Pixel clock
• Generated clock tolerance
• pll input divider
• pll feedback divider
• pixel clock divider
• character clock divider

Based on the above modeline should I be able to dervice these values or I need more information?