Custom HDMI Resolution on i.MX 8MP

[masalcp]

Hello everyone,
I want to display 3840x726@60 and 3840x1080@60 via HDMI, and it would be helpful if you could add the necessary HDMI PLL configuration to samsung_phy_pll_cfg[] in "drivers/phy/freescale/phy-fsl-samsung-hdmi.c".

Thank you.

[Bio_TICFSL]

Hello,

To achieve 3840x726@60 and 3840x1080@60 via HDMI, rhe exact HDMI PLL configuration for the samsung_phy driver depends on your specific driver version, but you will need to adjust the Pixel Clock (PCLK), Dot Clock, or TMDS (Transition Minimized Differential Signaling) Clock to match the required data rate for the selected resolution and refresh rate. 

1. Determine the Required Bandwidth

First, calculate the total pixel rate (or dot clock) for each resolution:

• 3840x726@60Hz: (3840 * 726 * 60) / 1,000,000 = ~167.96 MHz
• 3840x1080@60Hz: (3840 * 1080 * 60) / 1,000,000 = ~248.83 MHz

2. Find the samsung_phy_ Driver Configuration

• Locate the samsung_phy_ driver source code:

  You will need to find the relevant driver files (e.g., drivers/phy/samsung/ in the Linux kernel) to see how clocking and PLLs are controlled.
• Examine existing PLL configurations:

  Look for functions related to clock generation or PLL setup within the driver.

3. Adjust the PLL Configuration  and set the dtb

• You will need to find the appropriate registers within the samsung_phy_ driver that control the PLL (Phase-Locked Loop) or Clock Controller.
• Set the PLL to generate the correct PCLK: based on your desired resolution

Regards

[masalcp]

Hello,

I'm working on a project using the Yocto Scarthgap release, and I'm trying to enable a custom HDMI resolution of 3840x1080 @ 60Hz.

The required pixel clock for this mode is 266.64 MHz. To support this, I have added the following entry to the samsung_phy_pll_cfg[] array in the drivers/phy/freescale/phy-fsl-samsung-hdmi.c file:

C

{ 
    // 3840x1080@60Hz (266.64 MHz)
    266640000, {
        0x00, 0xD1, 0x6B, 0x15, 0x89, 0x05, 0x88, 0x45,
        0x4F, 0x30, 0x33, 0x65, 0x30, 0xB8, 0x24, 0x80,
        0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
        0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
        0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
    },
},

However, after applying this change and booting the system, I get no output on the display (a black screen). I suspect that these PHY PLL register values are incorrect for my hardware.

My main question is: Is there a PLL configuration tool available that can generate the correct register settings for the Samsung HDMI PHY for a given clock rate?

Please note that I cannot simply use the latest phy-fsl-samsung-hdmi.c driver from the mainline kernel, as it causes build errors within my current Yocto Scarthgap environment.

Any advice or suggestions would be greatly appreciated.

Thank you.

[Bio_TICFSL]

Hi,

The PLL is crucial for generating the necessary clock frequencies for the HDMI serializer, which serializes parallel data into a high-speed serial stream for HDMI output. In phy-fsl-samsung-hdmi.c, the PLL is configured with parameters (often stored in a Look-Up Table or LUT) to match the specific pixel clock required by the display, as seen in discussions about adding new modes and adjusting PLL settings for different resolutions like

2560×14402560 cross 1440

2560×1440

and

1920×12001920 cross 1200

1920×1200

. 

How the PLL is used:

• Clock generation:

  The PLL takes reference clocks (like APB and reference clocks) and generates the precise clock frequencies needed for the HDMI serializer to operate correctly. 
• Configuration for different modes:

  To support various video modes, the driver needs to configure the PLL with specific parameters for each supported pixel clock frequency. This is often handled by a Look-Up Table (LUT) containing the necessary settings. 
• Driver and hardware interaction:

  The phy-fsl-samsung-hdmi.c file contains the code that configures the hardware PLL, which is a part of the Samsung HDMI PHY, to meet the required timing and clocking specifications for the display to function. 
• Driver development:

  There are ongoing efforts to extend the driver's capabilities by adding support for more modes and fine-tuning the PLL settings, as shown by recent patches adding new LUT entries and adjusting PLL lock detection mechanisms

  Regards

[masalcp]

Hi,

I referred to samsung-hdmi-phy-pll-calculator and the phy-fsl-samsung-hdmi.c file from lf-6.22.y, and added a new entry to the static const struct phy_config phy_pll_cfg[] array accordingly.

As a result, the display output is now working correctly.