Cold Boot Crash at .925V VDDARM_IN level

[amiller]

We had an issue with i.MX6 automotive quad core crashing during boot but only when cold (a few boot crashed as warm as 10C to 15C) and when VDDARM_CAP dropped from 1.2V (792MHz) to .925V (assume 396Mhz while IO was being set up).  Also crashes during the same .925V condition on power down.

Found that reducing VDDARM_IN and VDDSOC_IN voltages from 1.475V to 1.3V have significantly lowered the temperature at which crashes occur.   

I'm not sure this fixes the issue correctly since the condition for VDD_CACHE_CAP must be less than 200mV above VDDARM_CAP is violated with either VDDARM_IN supply level during the crash periods (when LDO is at .925V).    

Why is reducing the VDDARM_IN and VDDSOC_IN input levels making a difference at the temperature that the boot crashes occur?

Appreciate any insight into why this works or other ways to address the issue.

Thanks

Alan M

[amiller]

Currently the CPU is running on internal LDOs and does not adjust the PMIC output levels.   When we reduce VDDARM_IN to boot colder we are reducing the overhead voltage for the LDOs.  We've set VDDARM_IN & VDDSOC_IN to 1.35V to lower the boot crash temperature to about -3C.  Still not sure why it works.  MMPF0100 PMIC outputs are configured to deliver max current.

We have also adjusted the DVFS lower frequency voltage setting higher to remove the VDD_CACHE_CAP - VDDARM_CAP > 200mV violation.   This really helps and allows booting down to -18C without issue (much below our instrument requirement).   

Any additional info about these settings or the issue is appreciated.   We plan to go forward with these changes.

Thank you Igor,

Alan 

[igorpadykov]

Hi Alan

I am not sure if pmic is used in the case, but one can carefully check

power up sequence and observe with oscilloscope for any glitches on

VDDHIGH_*, VDD_SNVS_* lines. If after fail pressing por will lead to successful boot,

this may point to ddr initialization problems. Also one can try to extend por up to 0.8-1 sec.

Best regards
igor

[igorpadykov]

Hi Alan

for reliable reboot recommended to reset both pmic (with pwron signal) and
procesor (with por), as it is done on Sabre SD schematic spf-27392 p.21 U507 buffer.
Otherwise since cpu freq driver may lower VDDARM_IN level, if processor resets at this time,
it can be insufficient for reliable boot. Resetting pmic provides necessary voltages for
reliable (re)boot. Temperature issues may be related to incorrect drive strength settings.

Best regards
igor
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