Clarification on DRAM Chip Configuration Discrepancy - Seeking Community Insights

[vivekvix]

Hello Community,

We are currently in the midst of designing a board for a client, and we have encountered a configuration discrepancy related to a DRAM chip. The DRAM chip comprises two dies, Die A and Die B. Ideally, the lines of Bank A of the DRAM should be connected to the A lines of our i.MX8MP SOM, and Bank B should be connected to the B lines in our SOM, following the logical pairing.

However, in the schematic reference provided by NXP, we have noticed that the configuration is different. They have connected lines A of the DRAM to the B lines of our SOM, and vice versa.

We are seeking insights from the community to understand the reasoning behind this configuration. We are curious to know if there are specific technical reasons for this choice, or if it's a matter of compatibility with certain systems or applications. If any of you have experience with similar configurations or have insights into why this might be the case, we would greatly appreciate your input.

Furthermore, if any community members have suggestions on how we should proceed with our design, considering this configuration difference, we would be very grateful for your guidance.

Thank you in advance for your expertise and support. Your contributions are immensely valuable to us and our client.

[vivekvix]

Thanks @riteshmpatel for the clarification. It is greatly appreciated!

[riteshmpatel · Accepted solution]

Hi @vivekvix,

I hope you are doing well.
Please accept my apologies for the delay in response.

The reason to connect lines A of the DRAM to lines B of the processor and vice-versa is for ease of routing only in the PCB Layout.

One can use either of the configurations to proceed further with the design.

I hope it helps!

Thanks & Regards,
Ritesh M Patel