Lavi, good day !
As for the examples - some initialization is needed for EIM channels (CSx), except
the case, when EIM NOR flash is boot device ; here boot ROM provides (CS0) initialization.
But by default EIM channels are disabled (EIM_CSnGCR1[CSEN] = 0).
Some examples from the Reference Manual are below.
22.7.1.1 Intel Sibley Flash Asynchronous Mode Configuration
• WR32('EIM_CS0GCR1,'h00210081);
• WR32('EIM_CS0RCR1,'h0e020000);
• WR32('EIM_CS0RCR2,'h00000000);
• WR32('EIM_CS0WCR1,'h0704a040);
22.7.1.2 Intel Sibley Flash Synchronous Mode Configuration
Configuration used for 133 MHz synchronous access to flash:
// Set memory to synchronous read mode
WR16('CS0+('h5903<<1),'h0060);
WR16('CS0+('h5903<<1),'h0003);
WR16('CS0+('h0000<<1),'h00ff);
// Set EIM configuration to synchronous timing
WR32('EIM_CS0GCR1,'h50214225); // 133 MHz
WR32('EIM_CS0RCR1,'h0c000000); // 12 cycles on memory
Configuration used for 66 MHz synchronous access to muxed flash:
// Set memory to synchronous read mode
WR16('CS0+('h3103<<1),'h0060);
WR16('CS0+('h3103<<1),'h0003);
WR16('CS0+('h0000<<1),'h00ff);
//--------------------------------------------------------------------------
// Set EIM configuration to synchronous timing
WR32('EIM_CS0GCR1,'h5021122d); // 66 MHz
WR32('EIM_CS0RCR1,'h07000000);
~Yuri.