CLKO2 output problem

[avexwu]

Hi there,

I am using i.MX6Q. I want to use CLKO2 as the MCLK source of my camera. The steps I did are as followed.

1.    Setup Pad , set gpio3 as clko2 output pin

MX6Q_PAD_GPIO_3__CCM_CLKO2,              // setup gpio3 as output pin of clko2

2.    get/set osc_clk as parent clock of clko2, set rate, and enable clko2

        clko2 = clk_get(NULL, "clko2_clk");

        if (IS_ERR(clko2))

                printk("can't get CLKO2 clock.\n");

        new_parent = clk_get(NULL, "osc"); // in sabresd bsp source code, "osc_clk" is a wrong name, tested already

        if (!IS_ERR(new_parent)) {

                clk_set_parent(clko2, new_parent);

                clk_put(new_parent);

        }

        rate = clk_round_rate(clko2, 24000000);

        clk_set_rate(clko2, rate);

        clk_enable(clko2);

However, there is nothing on gpio_3 pin, no clock on CLKO2 output pin. It seems the I miss some steps.

I print out the register CCOSR,  MXC_CCM_CCOSR=0x010E000F (1 00001110 00000000 00001111)

It seems the value is correctly be set, but it did not function as it should be.

The same way I used is okay to enable/disable CLKO, any idea? I use SABRESD android bsp as my source code base.

thanks anyway

avex

[emilmyhrman]

I'm having the same problem. What was the bug you found?

regards,

Emil

[emilmyhrman]

Figured it out. Register IOMUXC_SW_PAD_CTL_PAD_GPIO03 is set wrong when using the macro MX6Q_PAD_GPIO_0__CCM_CLKO.

Change it to "IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, MX6DL_CCM_CLK0_PAD_CTRL)" and it should work.

[rohanbhargava]

How do I do this? I have been looking around but can't find the exact file to set this.

Could you please provide detailed instructions?

Thanks

[fangmingan]

dear avex& weidong,

   I encounter the same situation as you. But i didn't understand your solution? how did you fix the bug? avexwu weidong.sun

thanks a lot

Fangming

[avexwu · Accepted solution]

Just see this my old post.

Answer to myself , YES, it's a bug but not hardware.

[avexwu]

Anyone can help?

Is it a bug of i.MX6Q CPU?

[weidong_sun]

Hello,Avex,

Would you like to try like the following steps ?

(1)IOMUX ( what you did is correct)

(2)Make 24M clock output via GPIO_3 PIN

clk_set_parent(&clko2_clk,&osc_clk);

clk_set_rate(&clko2_clk,24000000);

Regards,

Weidong

[avexwu]

Hi Weidong,

thanks for your reply,

1. There are two clock out of i.MX6Q, clko and clko2. clko works fine, and its IOMUX is MX6Q_PAD_GPIO_0__CCM_CLKO

I am working on clko2 , IOMUX is as step 1 of my post listed above.

2. As step 2 of my post above, I use osc_clk at 24MHZ already.

Regards,

[weidong_sun]

OK, good job !

Regards,

Weidong