Bit Clock accuracy

[yehudastern]

Hi,

I'm using 2 TLV320AIC3106 codecs, connected to SSI1 and SSI2, and I recently changed the sampling rate from 44.1KHz to 48KHz.

The sampling rate of one codec is accurate, whereas the other one is always about 1.5% less than expected.

This happens before changing the sampling rate as well as after doing so.

i.e. the previous Bit Clocks of both codecs were: 1.411KHz / 1.39KHz,   and the updated Bit Clocks are:  1.536KHz / 1.511KHz.

This happens although both clocks are originated from the same oscilator, and although both codecs are configured exactly the same.

Is this a silicon or routing issue, or could it be a SW issue?

Regards,

Yehuda

[igorpadykov]

Hi Yehuda

this looks like hardware issue, may be caused by poor chip

soldering or power supplies noise. Also it may be useful to check for

jitter of oscillator signal at codec pads, as close as possible.

Best regards

igor

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[yehudastern]

Hi Igor,

I had checked this on several boards, including on an iMX EVB (actually Variscite EVB which includes an iMX SOM) connected to an external codec EVB from TI, and on all the PCBs the BIT clock measured at SSI2 was 1.5127MHz (±0.1%) instead of 1.536MHz.    So if the problem isn't related to poor chip soldering nor PWS noise/crosstalk nor clock jitter, could it be a silicon issue?

Thx,

Yehuda

[yehudastern]

Hello Igor,

Could you please advise regarding the SSI2 clock issue.

As I understand, it can only be related to an iMX silicon problem or (less likely) a routing problem in Variscite's SOM).

Please advise if there a related errata, and if not, please suggest if a workaround patch in the alsamixer code could be the solution

(i.e. such as converting the oversampling of (48KHz -1.5%) to 8KHz sample rate).

Thx,

Yehuda

[igorpadykov]

Hi Yehuda

there are no silicon errata for ssi bit clocks. Accuracy

can be affected by used crystal and pll from which

ssi derives clock. So you can check crystal and ssi clocks

with oscilloscope and reprogram plls value, if needed.

For example if you got 1.5127MHz instead of 1.536MHz, one can try

to reprogram pll, increase its value by factor 1.015 [1.536/1.5127].

For testing one can output clocks on CKLO1,2 pins

using CCM_CCOSR register.

Note if clock is produced externally, that is ssi is slave, then check

codec external crystal and whoever is producing this clock.

Best regards

igor

[yehudastern]

Hello Igor,

Both SSI clocks are produced internally from the same PLL4 source which is programmed to 688.128 MHz.

(This frequency is too much for my scope, so I measured PLL4/8 frequency through CLKO1 and the measured frequency was correct).

Increasing PLL4 value by 1.5% as you suggested will also increase SSI1 sysclock which is currently accurate.

Other than PLL4, all other clock divisions along the way cannot be changed by 1.5% resolution.

Please advise regarding the suggested workaround patch in the alsamixer code, or any other alternative.

Regards,

Yehuda Stern

[igorpadykov]

in master mode ssi bit clock is produced from SSI1 sysclock.

In slave mode - from external oscillator. Clock generation is described in

Figure 61-22. SSI Transmit Clock Generator Block Diagram

i.MX6SDL Reference Manual.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Typical SSI sysclock and divider values are given in

Table 61-7. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2,

so you can test clocks with these values.

~igor