Assign XTALOSC_REF_CLK_32K to GPIO1_IO03 (i.MX6ULL)

[eishishibusawa]

Dear Sir

I want to ask about the pin assignment.

I refer to IMX6ULLRM Rev. 1, 11/2017.

It is described at P4099 Table 60-1. XTALOSC External Signals.

I think that XTALOSC_REF_CLK_32K can be assigned to GPIO1_IO03(ALT3).

On the other hand, it seems that we cannot select ALT3 with SW_MUX_CTL[MUX_MODE].

P1571 32.6.10 SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control

Q1.

How can I allocate XTALOSC_REF_CLK_32K to GPIO1_IO03?

Best Regards,

Eishi SHIBUSAWA

[art]

Actually, both the Table 60-1 and Table 60-2 of the i.MX6ULL Reference Manual document are a kind of typo. The REF_CLK_32K signal has no out-of-the-chip routing on the i.MX6ULL processor.

Have a great day,
Artur

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[weidongzhou]

Hello, Artur

Are you from NXP/FSL technical support team? I am very surprised to hear that

REF_CLK_32K signal has no out-of-the-chip routing on the i.MX6ULL processor

Actually we has a customized i.mx6ull board which route this REF_CLK_32K signal to an external peripheral through pad ENET1_RX_EN(ALT 2). This signal works just well with our peripheral and the board is in pre-production stage now. 

Can you confirm that this REF_CLK_32K will be absent on pad ENET1_RX_EN(ALT 2) of chips with NXP/FSL future mass production batch ? Currently our in use batch is MCIMX6Y2DVM09AA.

Regards

Weidong

[weidongzhou]

Hello,

Could any NXP/FSL technical support people please help to clarify this question？

It is urgent and we can not push our i.mx6ull board to production stage with a non-exist feature.

Regards

Weidong

[art]

I'm going to verify this with R&D. Unfortunately, I'm not sure if it can be done quickly due to the Christmas holidays. Anyway, I'll get back to you as soon as I get any definite info.

Best Regards,
Artur

[weidongzhou]

Artur,

Thank you for the support and waiting for the answer.

Regards

Weidong

[art · Accepted solution]

The R&D have checked the RTL design sheets and verified that the REF_CLK_32K signal pin muxing options, listed in the "Muxing Options" table in the Section 4.1.1 on the Page 214 of the i.MX6ULL Reference Manual Rev.1 document, i.e. ENET1_RX_EN (ALT2 mode), GPIO1_IO03 (ALT3 mode) and JTAG_TCK (ALT6 mode), are all valid and available in the silicon.

Best Regards,
Artur

[weidongzhou]

Artur,

That is result what we expected! Thanks for sorting out.

Regards

Weidong

[eishishibusawa]

Dear NXP support member

Please reply this question.

Best Regards,

Eishi SHIBUSAWA