About the NAND Row address cycle setting with the SABRE-AI board

[yuuki]

Dear all,

We are going to use i.MX6DualLite.

And NAND Boot is used in our system.

We refer to the schematic of the SABRE-AI board.

  - SABRE-AI-DUALLITE-CPU2

    => SPF-28605_b1.pdf

This schematic assumes that MT29F64G08AFAAAWP is used as NAND Flash device.

According to Boot configuration of SABRE-AI, NAND Row address cycle is set to 4.

  Boot_CFG1[1:0]=10 (Row Address Cycles is 4)

However, Row address cycle of MT29F64G08AFAAAWP is "3".

<MT29F64G08AFAAAWP Datasheet>

http://pdf.datasheet.directory/datasheets-0/micron_technology/MT29F64G08AFAAAWP_A.pdf

I think that the setting of Row address cycle of SABRE-AI does not match MT29F64G08AFAAAWP.

Would you tell me the reason setting Row address cycle to "4" in SABRE-AI?

Best Regards,

Yuuki Murasato

[art]

Actually, setting the Row address cycle number boot parameter larger than the actual Row address cycle number of a NAND Flash device used has no matter for the boot process, since, anyway, all zeros address is latched to a NAND Flash device during initial boot. So, this Row address cycle number setting of 4 has been chosen just for convenience to use single setting for various NAND Flash devices.

Have a great day,
Artur

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