About specifications of REF_CLK generated internally with i.MX6SoloLite

[yuuki]

Dear all,

Would you tell me the specifications of REF_CLK generated internally?

We think about the configuration that REF_CLK is output by FEC_REF_CLK pin.
This is configuration explained in Figure 11-3 of IMX6SLHDG.

IMX6SLHDG.pdf (Rev1)
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf
- Figure 11-3. Internal reference clock(P.106)

We want to know the contents similar to specifications explained in "Table 52.RMII Signal Timing" of the data sheet.

IMX6SLCEC.pdf (Rev3)
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SLCEC.pdf
- Table 52. RMII Signal Timing(P.65)
(We understand that it is a timing specification of REF_CLK when it is input to FEC_TX_CLK pin.)

Best Regards,
Yuuki

[Yuri · Accepted solution]

Hello,

  Strictly speaking, jitter or accuracy parameters of internal PLLs are not specified.

The only specified parameters may be found in the Datasheet(s) in section “PLL’s
Electrical Characteristics”.  Nevertheless, we can refer to Table 1-14 (24 MHz crystal
tolerance guidelines) of the Hardware Development Guide, assuming stability (thermal,
voltage and other) of PLL output clock is fully defined by external crystal / oscillator,
and i.MX6 meets USB, PCIe, Ethernet clock specs. 

Have a great day,
Yuri

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