About connection of IMX7 and Memory device

[okamotosatoshi]

Hi There,

I want to check for IMX7.
I connect the IMX7 and LPDDR3.

①Can swapping other than the lower bits of the byte lane (Data bit) ?
　It is the contents of the following.
②Can swapping byte lanes (Data bit)?
　A.When using 32-bit memory, can swapping Byte lane 0 and Byte lane 3 ?
　B.Can freely swapping other byte lanes (Data lane 0/1/2/3)?
③Can swapping Address line?

//------------------------------------------------------------------------
For MCIMX6Q-SMART DEVICE PLATFORM
//------------------------------------------------------------------------
Using bit swapping for DATA bus to allow easy pcb routing.
When using data bit swapping the low order bit of each byte must reside at bit 0 of the byte.
The remaining 7 data bits can be swapped freely.
This restriction is for write leveling calibration.
Example D0 to D0 or D0 to D8, and D1-7 can be swapped.
When swapping byte lanes on 16-bit memories, remember to move the DQMx, DQSx, and DQSx_B signals for that byte lane.
//------------------------------------------------------------------------

Best regards
 - satoshi

[okamotosatoshi]

Hi, Yuri

Thank you for your advice.
Yuri's response and Reference circuit was very useful.
We are promoting board design according to the guidelines.
However, it is difficult to satisfy all the conditions.

Just as Yuri's advice, I Consider the simulation.

Very Thanks.

Best regards
 - satoshi

[okamotosatoshi]

Hi, Yuri

Thank you for your reply.

I would like to check some of the guideline contents.
Document Number:Hardware Development Guide for i.MX7Dual and 7Solo Applications Processors, Rev. 0, 07/2016

①Is the length of CLK a mandatory requirement?
②Is there timing constraint on between CLK and DQS?
③Is there timing constraint on between each byte lane?
　The ALTERA document has restrictions of within ± 20 mm between byte lanes.
　Document Number：DDR3 SDRAM Interface Termination and Layout Guidelines (AN-520-1.1)
https://www.altera.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/an/an520.pdf

Best regards
 - satoshi

[Yuri · Accepted solution]

Hello, Satoshi !

1.

  Most parameters really are not mandatory, but they are involved in signal

timing budgets considerations.

2.

  Strictly speaking, to design a high-speed bus, we have to analyze signal rise-

times and trace lengths to estimate timings or to see if some termination schemes
are needed (to avoid signal corruption because of reflections).

  In order to define termination scheme (and resistor parameters) for signal

termination scheme, the design (board) should be simulated using IBIS / SPICE

models for the device (i.MX7), also actual board trace lengths should be

estimated too.

  Generally, alas, it is hard to give reasonable advises from rules of thumb,

nevertheless, many app notes are intended to help users in design (without

simulation). Therefore, for assurance, most reliable recommendations are

provided and, as result, they are very hard for realization.

  So, as a resume :

A) Please try to provide scheme simulation - if possible.

B) We can rely on design rules if simulation is not available.

3.

  Perhaps it would be easier to use Table 20 (DDR3 Routing by byte group)

of the Design Guide.

Regards,

Yuri.

[Yuri]

Hello

  Strictly speaking LPDDR3 spec does not allow swapping any pins.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[okamotosatoshi]

Hi, Yuri

Thank you for your reply.

What's mean for 「Strictly speaking」?

It is difficult to match with the DDR Routing Rules in the guideline.
Please tell me if there is a possibility of swapping.

Best regards
 - satoshi

[Yuri]

Hello,

  You may use Warp7 design as example.

Regards,

Yuri.