About POR_B signal.

[takashitakahash]

Hi community.

Our customer has below three questions.The understanding is correct?

(1) internal POR_B signal generation circuit detects the two types of supply voltage below.

- VDD_SOC_CAP

- VDD_HIGH_IN

Is it correct?

(2) when using common VDD_ARM_IN and VDD_SOC_IN

Also VDD_ARM_CAP and VDD_SOC_CAP is to De-assert the external POR_B signal before the operation guarantee voltage reaching, internal POR_B signal is substantially alternative.

Is it correct?

(3)As a condition of internal POR_B signal to De-assert,

After VDD_HIGH_IN after stabilization 4 [ms] elapsed, and VDD_SOC_CAP after stabilization 1 [ms] has been described ,

And if  common  of the VDD_HIGH_IN and VDD_SNVS_IN these RTC oscillation stabilization time is added.

Is it correct?

Thanks,

Best.

[Yuri · Accepted solution]

Hello,

  i.MX6 internal PMU, powered via VDD_SNVS_IN, controls generation of the
POR, based on the power supplies, as it described in section 60.5 (Power-On Reset
and power sequencing)  of i.MX6 D/Q RM (IMX6DQRM, Rev. 3, 07/2015) :
"The internal POR_B signal will be held low until all of the following conditions are met:

• 4ms after the external power supply VDDHIGH_IN is valid

• 1ms after the VDD_SOC_CAP supply is valid

The 4ms and 1ms delays are derived from counting the 32kHz RTC clock cycles; the

accuracy depends on the accuracy of the RTC". And RTC stabilization time should be added

here.  Also, let me remind, VDD_ARM_CAP is involved in POR considerations because
of power up sequence requirements.

Have a great day,
Yuri

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[takashitakahash]

Hello Yuri.

I have additional question.

With the previous answer, there is a question of the following two points.

①How many mini sec or micro sec RTC oscillation(32KHz x'tal  use) stabilization time?

If the common VDD_HIGH_IN and VDD_SNVS_IN, What number is time that the internal POR_B signal to De-assert?

② "In addition, VDD_ARM_CAP as notes will be involved in the notes Power up sequence of POR" Although I received your answer,

What things specifically any notes? Would you please supplementary explanation.

[Yuri]

Hello,

1.
  Crystal stabilization time depends on the crystal itself and may take several hundreds of msec.

And again : "the internal POR_B signal will be held low until all of the following conditions are met:

• 4ms after the external power supply VDDHIGH_IN is valid

• 1ms after the VDD_SOC_CAP supply is valid".

2.

From i.MX6 Datasheet(s), in particular - section 4.2.1 (Power-Up Sequence) :

"If the external SRC_POR_B signal is used to control the processor POR, then SRC_POR_B must

be immediately asserted at power-up and remain asserted until the VDD_ARM_CAP,

VDD_SOC_CAP, and VDD_PU_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN

may be applied in either order with no restrictions."

Regards,

Yuri.