ADMA LPUART0 Interrupt Configuration on the iMX8X Module

[Alexxis_04]

Requirement:

Configure the Rx_Data_Register_Full Interrupt for ADMA LPUART0 on the CM4 core.

Here's what I've tried:
All A35 cores have been disabled via U-Boot, so only the CM4 core is active.
ADMA LPUART0 operates correctly in polling mode for both reading and writing.
Although the interrupt has been configured, it is not triggering.

Questions:

How can this issue be resolved?
Could you please provide an example code for configuring this interrupt? (Note: An example for the CM4 dedicated UART is not needed.)
Is it necessary to configure IRQSTEER for this interrupt? If so, when and where should IRQSTEER be configured? Please include a demonstration code if possible.

Current Code Snippet:

LPUART_EnableInterrupts(ADMA__LPUART0, kLPUART_RxDataRegFullInterruptEnable);
EnableIRQ(ADMA_UART0_INT_IRQn);
NVIC_SetPriority(ADMA_UART0_INT_IRQn, 0x07);

#imx8x #UART_Interrupt
@kerryzhou 

Thanks and Regards

Alexxis

[Manuel_Salas]

Hello @Alexxis_04 

I hope you are doing very well.

Apologies for the long delay.

It appears, yes, the IRQSTEER should be configured.

Please take a look t the lpuart_edma_transfer.c of SDK 2.9.0:

 /* Enable interrupt in irqsteer */
    IRQSTEER_Init(IRQSTEER);
    IRQSTEER_EnableInterrupt(IRQSTEER, ADMA_UART0_DMA_RX_INT_IRQn);
    IRQSTEER_EnableInterrupt(IRQSTEER, ADMA_UART0_DMA_TX_INT_IRQn);

Also, keep in mind that Receive Data Register Full Flag behavior:

So, you can try to disable the FIFO or set the Watermark to 0.

I hope this information can helps to you.

Best regards,

Salas.