8MHz clock generate out using PLL in i.mx6ull maximum possibilities pins in processor

[prabhu1]

Hi Igorpadykov,

Other than CCM_CLKO1,2 any other PLL pin possibilities to generate 8MHz clock out.

In above image CCM_CLKO1,2 are connected JTAG pins(JTAG_TMS and JTAG_TDO) Since JTAG  pins N15 or P14 has been used for 8MHZ clock, will that be conflicting when we use JTAG. So any other pins for 8MHz clock generate.

[prabhu1]

But I didn't see any clock divider option on a sec.18.7.18 for 8MHz

[igorpadykov]

one can try to output AUDIO_PLL (reprogram it to necessary frequency

using CCM_ANALOG_PLL_AUDIOn register) and dividers in AUDIO_DIV_LSB(MSB)

CCM_ANALOG_MISC2n.

Best regards
igor

[igorpadykov]

Hi prabhu

as another alternative one can consider LVDSCLK1 (CCM_CLK1_N, CCM_CLK1_P balls)

described in sect.18.7.18 Miscellaneous Register 1 (CCM_ANALOG_MISC1n) i.MX6ULL Reference Manual 

https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM 

Best regards
igor
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