使用的IMX6Duallite平台, 老化3天后出现黑屏现象(LVDS屏的数据线无波形),LOG提示timeout when waiting for flip irq。
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分析:
1 示波器测试LVDS_T0+/T0-,LVDS_T1+/T1-,LVDS_T2+/T2-,LVDS_T3+/T3- 数据信号无任何的波形,只有偏置直流电平,但测试LVDS_CLK+/CLK-信号幅度正常,频率65MHZ正常
2 软件分析LOG提示:timeout when waiting for flip irq,显示irq异常而返回。LOG见附件
(1) 软件加入:write /sys/module/galcore/parameters/gpu3DMinClock 3 待测试。
(2)看贵司论坛的补丁如下的修改是否适应改IC?修改也没什么效果 。
- imx6q_set_lpm(WAIT_UNCLOCKED);
+ //imx6q_set_lpm(WAIT_UNCLOCKED);
cpu_do_idle();
- imx6q_set_lpm(WAIT_CLOCKED);
+ //imx6q_set_lpm(WAIT_CLOCKED);
spin_unlock(&master_lock);
goto done;
(2 ) 看代码是ipu出了问题,ipu_pre_yres_is_small。查询网上有一些客户提出该问题给NXP,但没得到正面解决问题的补丁。如帖子(Re: mxc_sdc_fb fb.16: timeout when waiting for fli... - NXP Community)
max_lu
Contributor I
Hi,
Thanks to NXP's support team, this issue is solved. Please follow https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf. And this fix also been included in NXP's kernel
https://source.codeaurora.org/external/imx/linux-imx, branch imx_3.14.52_1.1.0_ga, commit id bbb48bbc88284f29c6980ee70373f91c7c86ff42 and 3f575c4967001c239634565c1327f4cc1a30b2c4.
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Which board are you using?
Which BSP are you using?
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android5.1
bsp linux 3.14.52
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IMX6Duallite
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IC screen printed as MCIMX6U7CVM08AC
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I have referred to this blog post before, but it cannot solve our problem
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Looking at the blog below, there were issues with handling them, but we couldn't find any relevant patches (https://source.codeaurora.org/external/imx/linux-imx)
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Thanks to NXP's support team, this issue is solved. Please follow https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf. And this fix also been included in NXP's kernel
https://source.codeaurora.org/external/imx/linux-imx, branch imx_3.14.52_1.1.0_ga, commit id bbb48bbc88284f29c6980ee70373f91c7c86ff42 and 3f575c4967001c239634565c1327f4cc1a30b2c4.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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You could find the commit from here:
https://github.com/search?q=bbb48bbc88284f29c6980ee70373f91c7c86ff42&type=commits
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Have you try the newer version of BSP?
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Looking at the blog below, there were issues with handling them, but we couldn't find any relevant patches (https://source.codeaurora.org/external/imx/linux-imx)
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Thanks to NXP's support team, this issue is solved. Please follow https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf. And this fix also been included in NXP's kernel
https://source.codeaurora.org/external/imx/linux-imx, branch imx_3.14.52_1.1.0_ga, commit id bbb48bbc88284f29c6980ee70373f91c7c86ff42 and 3f575c4967001c239634565c1327f4cc1a30b2c4.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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NXP's kernel https://source.codeaurora.org/external/imx/linux-imx, branch imx_3.14.52_1.1.0_ga, commit id bbb48bbc88284f29c6980ee70373f91c7c86ff42 and 3f575c4967001c239634565c1327f4cc1a30b2c4.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Hi,
Thanks to NXP's support team, this issue is solved. Please follow https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf. And this fix also been included in NXP's kernel https://source.codeaurora.org/external/imx/linux-imx, branch imx_3.14.52_1.1.0_ga, commit id bbb48bbc88284f29c6980ee70373f91c7c86ff42 and 3f575c4967001c239634565c1327f4cc1a30b2c4.
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IC screen printed as MCIMX6U7CVM08AC 。Which model does this IC belong to in the following list?
BSP already has the following patches by default, but the problem still exists.
patch:(if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {)
static inline bool cpu_is_imx6sl(void) { return __mxc_cpu_type == MXC_CPU_IMX6SL; }
static inline bool cpu_is_imx6dl(void) { return __mxc_cpu_type == MXC_CPU_IMX6DL; }
static inline bool cpu_is_imx6sx(void) { return __mxc_cpu_type == MXC_CPU_IMX6SX; }
static inline bool cpu_is_imx6ul(void) { return __mxc_cpu_type == MXC_CPU_IMX6UL; }
static inline bool cpu_is_imx6q(void) { return __mxc_cpu_type == MXC_CPU_IMX6Q; }
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
} else {
/*
* The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
* bug. Set the muxes to the requested values before registering the
* ldb_di_sel clocks.
*/
disable_anatop_clocks();
init_ldb_clks(np);
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
}