i.MX 93 Memory Compatibility Guide

[#1]

The purpose of this document is to provide extended guidance for the selection of compatible LPDDR4/4X memory devices that are supported by the i.MX 93 series of processors. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs.

The i.MX 93 series of processors supports different packages, and each have their own maximum supported LPDDR4/4x data rates. Please refer to the respective datasheets.

Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity.

NOTE: Some of the LPDDR4/4X devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low-speed operation is planned in the use case, please consult with the memory vendor about the configuration aspects and possible customization of the memory device so correct functionality is ensured.

LPDDR4/4X - Maximum Supported Densities

SoC	Max Data bus width	Maximum density	Assumed memory organization	Notes
i.MX 93 (i.MX 93xx)	16-bit	16 Gb / (2 GB)	single rank, single channel device with 17-row addresses (R0 - R16)	1, 2, 3

 

LPDDR4/4X - List of Validated Memories

The validation process is an ongoing effort - regular updates of the table are expected.

SoC	Density	Memory Vendor	Validated Memory Part#	Notes
i.MX 93	16 Gb/ (2 GB)	Micron	LPDDR4/4x: MT53E1G16D1FW-046 AAT:A  (Z32N) MT53E1G16D1ZW-046 AAT:C (Z42N)	7 4, 8
	8 Gb/ (1 GB)	Micron	LPDDR4/4x: MT53D512M16D1DS-046 AAT (Z11M)	4, 10
	16 Gb/ (2 GB)	Micron	LPDDR4/4x: MT53E1G32D2FW-046 AUT:B (Z42M)	4, 5, 10
	8 Gb/ (1 GB)	Nanya	LPDDR4: NT6AN512M16AV-J1I LPDDR4x: NT6AP512M16BV-J1I	4, 8
	4 Gb/ (512 MB)	Nanya	LPDDR4x: NT6AP256M16AV	4, 8
	16 Gb/ (2 GB)	Kingston	LPDDR4: D1611PM3BDGUI-U	4, 8
	16 Gb/ (2 GB)	Kingston	LPDDR4: C1612PC2WDGTKR-U	7, 9
	4 Gb/ (512 MB)	ISSI	LPDDR4: IS43LQ16256B-062BLI	4, 8
	2Gb / (256 MB)	ISSI	LPDDR4: IS43LQ16128A-062BSLI	4, 6, 8
	8 Gb/ (1 GB)	CXMT	LPDDR4/4x: CXDB4CBAM-EA-M	4, 9
	16 Gb/ (2 GB)	JSC	LPDDR4x: JSL4BAG167ZAMF	4, 8
	8 Gb/ (1 GB)	JSC	LPDDR4x: JSL4B8G168ZAMF-05x	4, 8
	4 Gb/ (512 MB)	JSC	LPDDR4x: JSL4A4G168ZAMF-05	4, 8
	2Gb / (256 MB)	Winbond	LPDDR4x: W66BQ6NBHAGJ	4, 6, 8
	8Gb / (1 GB)	IM (Intelligent Memory)	LPDDR4x: IM8G16L4JCB-046I	4, 11
	16Gb / (2 GB)	IM (Intelligent Memory)	LPDDR4/4x: IMAG16L4KBBG	4, 8
	4Gb / (512 MB)	Samsung	LPDDR4: K4F4E164HD-THCL	4, 8
	8 Gb / (1 GB)	AM (Alliance Memory)	LPDDR4X: AS4C512M16MD4V-053BIN	4, 8
	4 Gb / (512 MB)	ISSI	LPDDR4/4X: IS43LQ16256B-053BLI	4, 8
	8 Gb / (1 GB)	ISSI	LPDDR4/4X: IS46LQ16512B-046BLA2	4, 8
	32 Gb / (4GB) 16 Gb / (2Gb) usable by i.MX93	ISSI	LPDDR4/4X: IS46LQ32K01B-046BLI	4, 8

 

Note 1:

The numbers are based purely on the IP documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, SoC reference manual and on the JEDEC standards JESD209-4B/JESD209-4-1 (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.

Note 2:

Byte-mode LPDDR4/4X devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification).

Note 3:

The SoC also supports dual rank single channel devices therefore, 16Gb/2GB density can be also achieved by using a dual rank single channel device with 16-row addresses (R0 - R15).

Note 4:

The memory part number did not undergo full JEDEC verification however, it passed all functional testing items.

Note 5:

This is a dual channel x32 device. Since i.MX93 only supports 16-bit LPDDR4/X data bus, it can only interface with one of the channels and therefore, utilize only half of the device's density. As indicated in the table - the device has 32Gb/4GB density however, only 16Gb/2GB can be used. There is no functional problem with using only one channel of a dual channel device as the channels are independent in LPDDR4/4X. 

Note 6:

This is a new JEDEC 100 ball package, half the size of the standard 200 ball package. This 100 ball package has the same performance and functionality as the 200 ball package, and has the added advantage of being smaller and cheaper than the standard package.

Note 7:

This device has been EoLed by the manufacturer and has been updated by a new memory part number 

Note 8:

Part is active. Reviewed Nov 2025

Note 9:

Part is obsolete.

Note 10:

This device will be EoLed in Q2 24 by the manufacturer and will not be updated by a new memory part number

Note 11:

DQ eye marginalities were identified during TSA analysis. vTSA and stability testing did not identify any issues.