iMX8 mini Lvds

[NunoVilaca]

Hi.

I'm trying to build android 12 for a custom board, but I'm having issues with lvds parameters, so I wonder if anyone here can point me to the right path.

I'm using this configs:

	dsi_lvds_bridge: sn65dsi84@2c {
		compatible = "ti,sn65dsi83";
		reg = <0x2c>;
		ti,dsi-lanes = <4>;
		ti,lvds-format = <0>;
		ti,lvds-bpp = <24>;
		ti,lvds-channels = <1>;
		ti,width-mm = <217>;
		ti,height-mm = <136>;
		enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
		enable-panel-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds>;
		status = "okay";

		display-timings {
			lvds {
				clock-frequency = <71107200>;
				hactive = <1280>;
				vactive = <800>;
				hback-porch = <80>;
				hfront-porch = <48>;
				vback-porch = <15>;
				vfront-porch = <2>;
				hsync-len = <32>;
				vsync-len = <6>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};

		port {
			lvds_in: endpoint {
				remote-endpoint = <&dsi_out>;
			};
		};
	};

 I get image, but only the top bar is ok. The rest of the image is scrambled.

The panel timings are correct, as I get a correct image in poky-mickledore.

These are the default kernel arguments:

stack_depot_disable=on kasan.stacktrace=off kvm-arm.mode=protected cgroup_disable=pressure cgroup.memory=nokmem init=/init consoleblank=0 androidboot.hardware=nxp cma=960M@0x400M-0x1000M firmware_class.path=/vendor/firmware loop.max_part=7 bootconfig androidboot.vendor.sysrq=1 transparent_hugepage=never console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200 androidboot.console=ttymxc3 androidboot.primary_display=imx-drm androidboot.board=varsommx8mmini androidboot.bt_uart=/dev/ttymxc1 androidboot.bt_sdio=/sys/bus/mmc/devices/mmc0:0001/mmc0:0001:1/device androidboot.bt_firmware=BCM43430A1.hcd androidboot.bt_sdio_id=0xa9a6 androidboot.wificountrycode=CN

Can anyone see some issue with the configs? Some idea of what's going wrong here?

[Bio_TICFSL]

Hello,

I found that the u-boot sets the various parent clocks before boot, but the kernel don't overwrite this setting (the specification in clk-imx6q.c doesn't apply).

Specifically, testing with devmem2 after boot :

CCM_CS2CDR (0x20C_402C) -> 0x007206C1  //MMDC_CH1 enabled on LDB_DI0_CLK_SEL)

After recompiling the uboot, setting manually the parent to PLL5_VIDEO, the issue disappear, and the kernel manages to control the PLL to the correct frequency.

I've added in the uboot platform file (board/freescale/mx6sabresd/mx6sabresd.c

  /* Turn on LDB0,IPU DI0 clocks */

  reg = __raw_readl(&mxc_ccm->CCGR3);

  reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;

  writel(reg, &mxc_ccm->CCGR3);

  /* set LDB0 clk select to 000 (pll5) */

  reg = readl(&mxc_ccm->cs2cdr);

  reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);

  reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->cs2cdr);

  /* LDB clock div by 7 */

  reg = readl(&mxc_ccm->cscmr2);

  reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;

  writel(reg, &mxc_ccm->cscmr2);

  /* derive ipu1_di0_clk_root clock from ldb_di0_clk */

  reg = readl(&mxc_ccm->chsccdr);

  reg |= (CHSCCDR_CLK_SEL_LDB_DI0

  << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->chsccdr);

After boot:

CCM_CS2CDR (0x20C_402C) -> 0x007200C1  //PLL5_CLK enabled on LDB_DI0_CLK_SEL

Maybe the kernel fails to write the registers in the initialization process?

Regards