Standard Trusted Firmware‑M (TF‑M) targets in Zephyr, including RW61x‑based platforms, assume the presence of BL2 (MCUboot) as the second-stage bootloader. BL2 is responsible for image authentication, upgrade handling, and flash layout enforcement.
However, many NXP devices provide a ROM‑based secure boot / dual‑boot mechanism capable of authenticating firmware and directly transferring control to a secure image. In such cases, BL2 is redundant and can be disabled to reduce boot time and flash usage.
This article describes how to disable BL2 in TF‑M and configure Zephyr to boot directly from ROM into the TF‑M Secure image, followed by the Non‑Secure application.
The default Zephyr TF‑M boot chain is:
BootROM → BL2 (MCUboot) → TF‑M Secure → Non‑Secure application
BL2:
Example with samples/tfm_integration/config_build
When using the ROM bootloader:
BootROM → TF‑M Secure → Non‑Secure application
In this scenario:
Example with samples/tfm_integration/config_build
Disable BL2 explicitly in the project configurations and update the base address:
This removes MCUboot from the build and prevents generation of BL2 artifacts.
When BL2 is removed, the ROM must jump directly to the TF‑M Secure vector table.
Ensure that:
The TF‑M Secure image will transfer control after initialization.
On RW61x‑class devices, the ROM expects the Secure image to start at offset 0x1000 within a bootable slot, with the Non‑Secure image located at offset 0xA0000. Each boot slot therefore contains a complete Secure + Non‑Secure pair at fixed offsets.
The ROM authenticates the slot, jumps to the Secure offset, and TF‑M later transfers control to the Non‑Secure image.
BootROM
├─ Authenticate Slot 0 → Secure@+0x1000 → Non‑Secure@+0xA0000
└─ Authenticate Slot 1 → Secure@+0x1000 → Non‑Secure@+0xA0000
No BL2 or runtime image swapping is involved.
Each slot is independently bootable and contains no shared state with the other slot.
For each slot, the ROM expects:
slot_base + 0x1000The ROM never jumps to Non‑Secure directly.
First we'll create two images one for slot 0 and one for slot 1. The difference will be noted in the text of the non-secure image.
For each slot, build:
+0x1000)+0xA0000)Slot 0, I modified the non-secure image to print a quick message identifying the slot it was programmed in.
Slot 1, I modified the non-secure image to print a quick message identifying the slot it was programmed in.
Using the SEC tool, we will use the "Merge Tool" to merge the secure and non-secure binaries with the appropriate offset.
ROM expects one contiguous image per slot, not two independent binaries.
In SEC Tool:
0x10000xA0000* If you are using the kconfig options as described above, the FCB will be attached to the secure binary, therefore please ensure that your offset for secure binary considers the FCB location which is offset 0x400
Dual‑boot selection is driven entirely by ROM metadata.
For each merged image:
Example:
12ROM rules are typically:
Select the merged image for the slot you would like to program first. Select the version that will be used with that slot.
Next, open "Dual Image Boot"
For Slot 0, select "Image 0" and select the offset you would like to use for the slot division. For Slot 1, select "Image 1".
Expected behavior:
slot 0 + 0x1000
Expected behavior:
0x0 instead of 0x1000)
Disabling BL2 in TF‑M and booting directly from ROM is a valid, efficient, and production‑ready configuration when the device ROM already provides secure boot and dual‑boot services. In this architecture, the ROM is the authority for authentication, version selection, and rollback, while TF‑M Secure becomes the first executable firmware stage.
When combined with ROM‑managed A/B dual boot, this approach provides:
The key requirements for success are:
+0x1000)+0xA0000)In this model, TF‑M and Zephyr are slot‑agnostic: they do not manage upgrades, slot selection, or rollback. All boot decisions are made before execution begins, by the ROM, based on SEC‑provided metadata.
This design reduces boot time, simplifies flash layouts, removes firmware‑swap complexity, and aligns well with high‑reliability production systems where firmware updates are performed out‑of‑band and enforced by ROM‑level security.