he first access to the QSPI in "basic read operation", what combinations What kind of access mode? (Non-XIP or XIP) (Single or Dual or Quad), other

[takashitakahash]

typo

The first access to the QSPI in "basic read operation", what combinations What kind of access mode? (Non-XIP or XIP) + (Single or Dual or Quad), other

[naoumgitnik]

Hello Everybody,

Copying from another thread:

"... The first basic read command is performed as detailed in the table 30-428 ..., this reads back the 318 configuration bytes header stored on the flash itself, this is at 18MHz, 1-bit, SDR, there is no XiP or non-XiP here, it is purely using the basic read command, supported by all devices, the BootROM then uses these 318 bytes to configure the QuadSPI as required, see the table 19-12 in the boot section describing these bytes, which can be used to change bus width, speed, SDR/DDR as well as a bunch of other timing-related parameters.

Subsequent accesses are as set up by these 318 bytes, XiP/non-XiP is decided by the BootROM, dependent on the IVT start address..."

Regards, Naoum Gitnik.

[naoumgitnik]

Dear Takashi,

To expedite the process, may you refer us to the relevant chapter / table / diagram / etc. in our documentation, please?

Regards, Naoum Gitnik.

[kef2]

Hm, could you please elaborate on your request? It is not clear what you are asking about.

For first attempt to QSPI on bare metal, it is worth trying TWR-VF65GS10 getting started package:

http://cache.freescale.com/files/32bit/software/board_support_packages/TWR-VF65GS10-QSP.zip

Compiling hello_world for QSPI XIP, and then compiling quad_load to program hello_world to QSPI chip helped me a lot.

XIP or non-XIP depends on your speed and RAM requirements. XIP allows to save RAM space. Non-XIP improves performance, though it depends on how often instruction cache needs to be refreshed from code space. For few and rare I-cache misses, it doesn't make a lot of sense to non-XIP. Just try and see what suits you the best.