It should support all 8 and 16-bit NAND devices, the address is passed as a column/row pair as part of the protocol, there is support upto 16-bit column, 24-bit row addressing, please refer to the reference manual and the NAND datasheet you propose to use, also check the chip configuration chapter in the RM for implementation specifics on the NAND controller.
Boot from eMMC/MMC devices are also supported, again detailed in the RM, in the system boot chapter, see SD/MMC boot section for device configuration.
Ross