Share the CS signal

[keisukewatanabe]

When I use the QSPI0 in parallel mode.

The CS signal of serial flash connected QSPI0_A and QSPI1_B, is it necessary to connect common CS signal?

Status quo, are connected to the CS pin of each.

Best regards,

Keisuke Watanabe

[naoumgitnik]

Hello Karina,

Below is what I first planned to answer:

====================

Dear Keisuke,

I am still having difficulties understanding why you want to connect the PCSFA1 and PCSFB1 signals to each other?

May you also send me a fragment of your schematic with the 2 QuadSPI chips to better understand that?

Sincerely yours, Naoum Gitnik.

====================

but I am afraid there exists some language barrier here, and it makes sense to involve our Japan FAE for better communication.

Regards, Naoum.

[naoumgitnik]

Dear Keisuke,

I am having difficulties understanding your question.

• May you provide graphic illustrations for the options you prefer more and less, please? If you have access to our schematics, feel free to send their relevant fragments as examples.

• If possible, it would also help to refer me to the specific Vybrid device's pins being used in this case.

Sincerely yours, Naoum Gitnik.

[keisukewatanabe]

Dear Naoum,

Please see the Figure 30-420 of VYBRIDRM document.

Is it possible to common PCSFA1 and PCSFB1?

Best regards, Keisuke Watanabe

[YumotoTaku]

Hello, Karina-san and Naoum-san,

I add some comments to Watanabe-san's question.

Customer uses QSPI as parallel mode. They thought QSPI0_A and QSPI_B controls 2 QSPI Flash and QSPI0_A_CSn and QSPI0_B_CSn output same signal. So they would like to confirm whether each CS signals are controlled by QSPI0_A_CSn and QSPI0_B_CSn or only one of QSPI0_X_CSn can control both CS.

I think our recommendation is that each CS on QSPI flash is controlled by each CS on QSPI0. Is it correct? I add simple slide about this question, could you also confirm it?

Best Regards

Taku.

[naoumgitnik · Accepted solution]

Gentlemen,

Now I clearly understand the issue (thanks to Taku-san).

I agree with Taku-san that each CS should becontrolled separately for the reason that, even while in the parallel mode, each of the two QSPI controllers uses its own blocks and paths inside the chip with its own timing, not necessarily identical to that of the other controller.

Sincerely yours, Naoum Gitnik.

[keisukewatanabe]

Dear Naoum-san and Taku-san,

Thank you for your reply.

I am sorry for inconvenience.

Best regards,

Keisuke Watanabe