PLL2 Lock Setup

[soichiyamamoto]

Hi,

I have qustion about PLL2

After the exit of the LPSTOP3 mode, PLL2 does not rarely lock it.

I set PLL2 to 480MHz.

The matching of the crystal oscillator is comfirmed.

Q1)Does PLL2 of VF6xx support 480MHz?

Q2)What should I confirm?

Q3)Please give me advice as to what I should do from now on.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

Below is excerpt from the related thread lead by your FAE (Hang up issue from LPSTOP3 mode):

"... Until now, we have been trying to resolve several issues at once; what if we first, for the experimental purposes only, forget about retaining DDR data (i.e. Self-Refresh mode) and test waking up from LPStop with using DDR but without DDR data retention. - This way we will learn if the problem is related to the DDR data retention (code piece or chip operation) or not."

So, if you try configuring PLL2 the same way as though you do retain DRR data but without retaining, does it still show the PLL2 locking problem once in a while?

Sincerely, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

yes.

DDR clock use PLL2.

PLL2 unlocked it in front of DDR Setup.

I learned a this reality.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

1. Do you mean that the PLL2 locking issue occurs PRIOR TO the DDR memory controller initialization procedure?
2. Do you mean that the PLL2 locking issue occurs PRIOR TO the DDR retention ("out of Self-Reresh”) routine?
3. Have you tried to fully delete the Self-Refresh piece from the code to see if the PLL2 locking issue still occurs while waking up and configuring PLL2?

Regards, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

I will now answer your question.

Q1) Yes.

Q2) Yes.

Q3) No.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

Would that be difficult to try #3, please? - This way we would prove the Self-Refresh code piece is not the culprit.

Regards, Naoum Gitnik.