Maximum sink/source current value in Vybrid's datasheet

[Zwerg_nase]

What settings of the DSE bits correspond to the GPIO maximum sink/source current value (7 mA) in Vybrid's datasheet?

[naoumgitnik · Accepted solution]

Dorogoy Andrey,

There is no direct relationship between the maximum GPIO sink/source current values and DSE settings.

The 7mA value only means that a user has to limit the current externally, usually by using a series resistor (and based on Ohm's law), e.g. while lighting an LED. In this case, to minimize the internal heat dissipation, I would recommend selecting the lowest internal GPIO pad impedance.

In the LED use case, if the desired current is 5mA and the LED has a voltage drop over it of 1.8V @ 5mA, then the total series resistance should be (3.3V - 1.8V) / 5mA = 300 Ohms. If the lowest DSE setting is used (20 Ohms), then the external resistor's value equals 300 - 20 = 280 Ohms.

Uspehov v razprabotke!

S uvazheniem, Naoum Gitnik.

[Zwerg_nase]

Dorogoy Naoum,

Spasibo za otvet!

I understand that 7 mA is the maximum value of the DC current, so in case of an AC current, the maximum output current value can be increased (depending on switching frequency, duty value, etc.)?

S uvazheniem,

Andrey Pavlenko

[naoumgitnik]

Vsegda pozhaluysta, Andrey! :smileyhappy:

I guess you are talking not about real AC signal out of a GPIO pin but rather a signal toggling between 'logic 0' and 'logic 1' at some frequency / duty cycle.

The major aspect causing IC pin limitation is the Joule heating (remember the Joule's law_ - you and I know it as the Joule-Lenz's law) applied to the bond wires, i.e. quite thin wires connecting the silicon die to the IC package pins/balls. If current in a wire (even when the die itself allows for that) is too high, it simply melts it, so it is required to keep the average (actually, root-mean square) current within the limits - and this answers your above question about the IO output current while toggling.

Another limitation is with the power/ground pins; notice, the current flowing out of the chip's IOs flows into the chip through them, and they should not melt either. This is why it is not allowed to draw max. current out of all the IOs simultaneously - it would easily exceed the power/ground pins' limit but luckily such a scenario practically never happens (most likely your use case in not even close to it...).

S uvazheniem, Naoum Gitnik.

[Zwerg_nase]

Dorogoy Naoum,

Yes, I was meaning a maximum current value for the toggling GPIO pin.

Do you think that it would be safe using the following formula

Imax = 7 mA / (square root (Duty), where Duty = toggling pin current pulse ratio.

as an estimate for the maximum current through a togging GPIO pin?

S uvazheniem,

Andrey Pavlenko

[naoumgitnik]

Dorogoy Andrey,

Your approach of taking the signal duty cycle into account is absolutely correct.

Unfortunately, the formula is not linear, e.g., if for half of the period the current is 10mA and 0 for the other half, then total of I² over the entire period is (10² /2 + 0² /2) = 50, square root of which approximately equals 7.1mA. ßThis is the value to be compared to the max. DC value for the IO pin.

S uvazheniem, Naoum Gitnik.

[Zwerg_nase]

Dorogoy Naoum,

I have a slightly different use case: GPIO of Vybrid is connected to a CMOS input of another IC with quite negligible input current. So the maximum output current of Vybrid's GPIO is sourced/sinked during charging/discharging of the input capacitance of that another IC (several pF). The charge/discharge time (t) is about several ns. For the GPIO toggling period = T (tens of ns), I believe that the Duty value in the formula above  = (2*t)/T, because charge or discharge happens each T/2. What do you think?

S uvazheniem,

Andrey Pavlenko

[naoumgitnik]

Dorogoy Andrey,

Unless I am missing something in your description, having a CMOS input as a load is very typical for a GPIO (i.e. what all chips are designed for), so no Joule heating problem in your case, i.e. when current essentially flows while toggling only.

S uvazheniem, Naoum Gitnik.

[Zwerg_nase]

Dorogoy Naoum,

Yes, I understand that driving a CMOS input should not be a problem for Vybrid's GPIO. My goal (I need this for a stress analysis report of our device) is to assess the maximum current sourced/sunk by a toggling Vybrid's GPIO which is connected to a CMOS input, and make sure that it is allowed by Vybrid's datasheet. The problem here is that this current (tens of mA), calculated as shown above for the charge/discharge of a capacitive load, is substaintially greater than the maximum current given in Vybrid's datasheet (7 mA). So my point here is that for such cases you need to compare that 7 mA value with an averaged value of the toggling GPIO sunk/sourced current rather than with the maximum value of the toggling GPIO sunk/sourced current.

S uvazheniem,

Andrey Pavlenko

[naoumgitnik]

Yes, Andrey, your point is correct.

/Naoum G.

[Zwerg_nase]

Spasibo, Naoum)

S uvazheniem,

Andrey Pavlenko