I am now using TWR-VF65SG10, and I try to measure the cycle time of MCC cpu-to-cpu interrupt,
How much cycle it takes between M4 triggers an interrupt and A5 receives an event?
Since I can't use Streamline, and SSH into the target board, is there any way I could measure the cycle time or can some provide me a number ?
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I've read your comments, I have a few question
1. Are those number of first comment from AN4947 ?
2. You mentioned that the conclusion of 664 MB/s is based on theory, is that the result of calculation of those number mentioned above?
3. How did you get the number of 7MB/s ? is that a real target board's result ?
Hello a a,
1. Yes. Also those numbers come from designers.
2. Yes. It is theoretical throughput of HW - more in the thread.
3. It was real test on real board (debug target, release can be faster as mentioned in the thread).
For third question, can I get more detailed information?
Like how much time does it spend on semaphore locking, and interrupt handling?
If I have only ARM energy probe and CMSIS-DAP from board, how can I do in DS-5 to get that more information?
Hello a a,
the test details are here https://community.nxp.com/thread/384093#comment-612762
Semaphore is peripheral like any other. Please check AN4947. For interrupt handling please look at ARM Information Center
To measure event you can use internal timers of ARM or you can use GPIO toggling + oscilloscope.
As far as I checked the reference manual contains no information regarding the CPU to CPU cycle time. And I am not aware other than streamline how to find the cycle time. To make us understand the problem could you please tell us why you looking for cycle time?
I want to know the overhead of CPU to CPU interrupt, when one core tries to use the MCC API to trigger the interrupt to the other core.
Is the overhead of triggering hardware interrupt is too small to be neglected, then I can just calculate the API execution cycle time?