In the dual core VF6 can I only boot the m4 core to minimize system power in certain applications?

[kenmcdaniel]

Few questions on the VF6xx cores:

Can I only boot the m4 core (keeping the A5 off or stopped) in the VF6xx  to minimize system power in certain applications?

Will the m4 core have access to the nand and ddr controllers if the A5 core is off?

What are typical power measurement in low power modes if the m4 is running and the A5 core is off/stopped?

Thanks,

Ken

[alejandrolozan1]

From the below thread:

Hi, the answer depends on which core is the primary one. If A5 is the primary core, then you could you could put the core into one of the three LPStop modes. If A5 is the

secondary core, you can disable it with writing '0x5A5A' into CCM_CCOWR register.

Re: Re: Need a code sequence to shutdown the Cortex A5 core

Best Regards,

Alejandro

[swapnilv]

Hi,

I am not able to access the link mentioned by you

Re: Re: Need a code sequence to shutdown the Cortex A5 core

https://community.freescale.com/message/423803#423803

I get below message when I try to access the link.

"Access to this place or content is restricted. If you think this is a mistake, please contact your administrator or the person who directed you here."

[alejandrolozan1]

Sorry, what it matters is that if A5 is the primary core, then you could you could put the core into one of the three LPStop modes. If A5 is the secondary core, you can disable it with writing '0x5A5A' into CCM_CCOWR register.

Best Regards,

Alejandro

[swapnilv]

Hi,

Any updates for the questions that I have asked previously regarding disabling primary A5 Core and how to put it in LPstop mode?

Thanks in advance..

Swapnil

[alejandrolozan1]

Hi,

You can find code that explains in detail how to change from one power mode to another in the baremetal sample code:

Sample Code for Vybrid Controller Tower System

I think you may find it very useful.

Best Regards,

Alejandro

[kenmcdaniel]

Hi,

We have the dual core A5/M4 Vybrid Controller Tower System and the sample code does not put the A5 in LPSTOP. Is there a problem with the sample code?

-ken

[alejandrolozan1]

The LPSTOP mode will enter until both cores execute the "wfi" instruction. If CA5 executes the wfi, this will halt  but the entire system (SoC) will not mode to LPSTOP mode. 

/Alejandro

[karina_valencia]

alejandrolozano please continue with the follow up.

[karina_valencia]

alejandrolozano​ any  update?

[swapnilv]

Thanks for your reply..

I am using pcm052 PhyCORE-Vybrid development kit which has A5 as primary core.

What I want to do is disable A5 core completely and only run MQX applications on M4 core.

So my question is:

1. Does "Putting A5 into LPstop mode" means there is a software mechanism for this and A5 will be completely disabled and I will be able to boot the board with M4 core only?

2. Could you please guide me how I can put A5 into  LPstop mode?

3. Do I need to make any changes in uboot bootloader if I wish to disable A5 core and boot directly from M4 core MQX application?

Thanks in advance,

Swapnil

[karina_valencia]

alejandrolozano​ please check it

[karina_valencia]

timesyssupport​ can you help here?