I encountered some issues writing to a memory that we allocated to be shared both the A5 and M4.
When I write to the shared memory in A5, not all data is being reflected immediately. It will only reflect when we tried to rewrite the data again.
Here is a scenario of what i am doing.
1. mmap the /dev/mem
2. update data in the shared memory
3. read in the M4.
Result: not all are reflected.
4. rewrite again in A5.
5. read in the M4.
Result: all are reflected.
We have similar experience in M4 and we solve it by calling _DCACHE_FLUSH_MLINES(). to flush the data after writing.
Does anybody know what would be the equivalent for flushing DCACHE in A5?
Solved! Go to Solution.
As suggested in the ticket you have open with our Support Engineers, MCC_DECACHE_INVALIDATE_MLINES may be what you are looking for, you can refer to https://linuxlink.timesys.com/system/files/Vybrid_mcc_design.pdf for further insight/examples.
Alternatively, reviewing arch/arm/mm/cache-l2x0.c, you will see the 'l2x0_flush_all()' function, which will flush the entire L2 cache.
Currently I am not using the MCC and the A5 application is a userspace not in the kernel.
I used mmap to map the memory.
I found a site that calls a clear cache. __clear_cache() to flush and invalidate the cache but still not working or I missed some prerequisite.
Does this function not satisfy your needs:
arch/arm/mm/cache-l2x0.c, 'l2x0_flush_all()' function
I don't believe this is possible from userspace; most discussion I can find along these lines suggest a kernel driver to flush cache, as userspace would not have permission to modify memory.