Drive Strength Field specification

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Drive Strength Field specification

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mplseng
Contributor II

I need to set the drive strength for some DDR pins to 40 ohms. The Vybrid manual does not explicitly specify the correct setting for selecting 40 Ohm if DDR.

Should  I use 110 for 40 Ohm if DDR?

This is the excerpt from the manual

Vybrid Reference Manual, Rev. 7, 06/2014, p.221

     Drive Strength Field. Select one of the following values for pad: PTA6.

     000 output driver disabled;

     001 150 Ohm (240 Ohm if pad is DDR)

     010 75 Ohm (120 Ohm if pad is DDR)

     011 50 Ohm (80 Ohm if pad is DDR)

     100 37 Ohm (60 Ohm if pad is DDR)

     101 30 Ohm (48 Ohm if pad is DDR)

     110 25 Ohm

     111 20 Ohm (34 Ohm if pad is DDR)

Thanks

Bob

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jiri-b36968
NXP Employee
NXP Employee

Hi Bob,

it is design specific: Trace length, PCB, memory. Nevertheless on TWR-VF65 rev.H (SDRAM and Vybrid are next to each other, without external termination) we are using DSE = 110. See below:

void setup_iomux_ddr(void)

{

#define DDR_IOMUX    0x00000180

#define DDR_IOMUX1    0x00010180

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CLK);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D15);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D14);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D13);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D12);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D11);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D10);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D9);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D8);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D7);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D6);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D5);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D4);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D3);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D2);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D0);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQM1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQM0);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0);

}

/Jiri

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jiri-b36968
NXP Employee
NXP Employee

Hi Bob,

Yes 0b110 correspond to 40 Ohm for DDR case. Confirmed by designers. Sorry for missing information in RM.

/Jiri

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jiri-b36968
NXP Employee
NXP Employee

Hi Bob,

it is design specific: Trace length, PCB, memory. Nevertheless on TWR-VF65 rev.H (SDRAM and Vybrid are next to each other, without external termination) we are using DSE = 110. See below:

void setup_iomux_ddr(void)

{

#define DDR_IOMUX    0x00000180

#define DDR_IOMUX1    0x00010180

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CLK);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D15);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D14);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D13);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D12);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D11);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D10);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D9);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D8);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D7);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D6);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D5);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D4);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D3);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D2);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_D0);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQM1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQM0);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1);

    __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1);

    __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0);

}

/Jiri

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mplseng
Contributor II

I asked the question incorrectly. I want to use 40 ohm drive strength. Does the drive strength setting of 110 correspond to 40 Ohm if DDR selected?


Bob


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