DDR3 Reinitialization

[johnfielden]

I have a question regarding the initialization of the DDR SDRAM memory controller in the VF6.   Our product does not use Linux, but uses a small RTOS instead.  There is 128Mbytes of DDR3 memory tied to the VF6 in our design, but that is dedicated to processing data packets.   During the periods between data packets (on the order of minutes) we need to lower the power consumption as much as is possible to meet battery life requirements.

Our intention is to turn off the DDR3 memory voltage rail when the DDR3 is not needed.  That means that the RTOS will run entirely out of the VF6’s internal RAM.   This also means that when the DDR3 is turned back on that the VF6 will have to reinitialize the DDR controller.   We were told by a Freescale FAE that we could turn the DDR voltage rail on and off without issue (though that may just have meant without damaging the part).

The VF6 controls the DDR voltage rail with a GPIO signal in our design.  This is different than the Tower or Phytec boards which always power the DDR memory.  We’ve changed the Tower initialization code sequence to include turning on the DDR3 memory.  We have found that the DDR voltage needs to be turned on prior to initializing the DDR clock domain.  Also, we’ve found that some amount of time is required from when the DDR clock is enabled and the DDR controller is enabled ( DDR_CR00[START] is asserted).   My first questions are what kinds of delays we should be using between turning on the DDR voltage rail, enabling the clock, and enabling the DDR controller, or if there are any other dependencies that we should be aware of?

Beyond power on initialization, we’ve been trying to get the memory controller to work when powering the DDR down and back up without a system reset.  The following code describes the current memory test that we are trying to do to prove that we can power cycle the DDR independently of the VF6: 

setup_gpio_pins(); // Setup the GPIO pins

  while(!status) {     // run memory tests until we fail.....

    reg32_write(0x400ae400, 0x00000600); //DDR_CR0 = Stop the DDR Controller...

    clear_ccgr_register(DDRMC_CCGR_INDEX); // disable DDR Controller clock gate

    ddr_power(0);      // DDR off

    time_delay_ms(10); // Sleep 10 ms

    ddr_power(1);      // DDR on

    time_delay_ms(10); // Sleep 10 ms

    ddr_init2(CLK_ON_ALL_MODES);   // re-initialize the ddr controller...

    time_delay_ms(10); // Sleep 10 ms

    status = memtest_vybrid_ddr();// Here’s where we fail….

    count++;

  }

This code fails miserably every time.  We commented out the ddr_power(1) and ddr_power(0) statements to eliminate the actual power cycling and found that the controller was flakey at best, sometimes passing our memory test, sometimes not.  Failures varied from data bit tests, to address bit testing. 

Looking at the DDR controller documentation, we see the following passage: 

“34.7 Initialization and Application Information

The memory controller requires a sequence for correct operation after power to the

microcontroller and memory devices is stable. When power is stable, the memory

controller automatically initializes the memory devices.

The procedure to initialize the memory controller is as follows:

1. Assert system reset (managed by device logic) and wait for the reset to get

deasserted.

2. Issue write register commands to configure the DRAM protocols and the settings for

the memory. Keep the DDR_CR00[START] de-asserted during this initialization step.

3. Assert the DDR_CR00[START]. This triggers the memory controller to execute the

initialization sequence using the bits written into the registers.

The MC will set the initialization complete interrupt (bit 9) in the

DDR_CR80[INT_STAT] when it is ready for commands. In addition, the user should

check that the CCM_CCSR[DDRC_CLK_SEL] is enabled before accessing the DDR memory.”

Which indicates that what we are trying to do is not possible without a full system reset, a full system reset would cause other problems in our system.  Is there another way to get the DDR controller reset properly?  Is there something else we should be doing to allow us to power cycle the DDR controller and memory without power cycling the entire VF6?

Thanks,

John Fielden

[naoumgitnik]

Hello John,

Your configuration is a bit unusual... and might need a tricky solution...

How about powering the DDR memory off but not the controller? - If after powering the memory back on everything works, try to also disable the clock(s) used by the controller - in this case, its power consumption is very low, only caused by the CMOS leakage currents. With the clock(s) enabled again, the controller quite likely will continue from the point it was halted on (i.e. without re-initialization).

Please, let me know if this approach works.

Regards, Naoum Gitnik.

[johnfielden]

The 1.5V plane feeding the DDR controller and the DDR3 memory is not seperable in our design.  It's an inner plane and ties many vias together.  We've attempted your second suggestion, disable the clocks to the controller.  This seems to work and appears to give a power savings of 70% (of just the DDR power).   I'm checking with Micron (the DDR3 vendor) , but I'm wondering how this "sleep" state compares to self refresh mode.  If they are similar then we arn't really saving anything by shutting off the clocks. 

Which begs the question, what do we need to do to get into self refresh mode?  Our software engineer is looking into this.

Additionally, one of the questions from my first post seems to have been missed.

How much time delay is required between when the DDR voltage rail is turned on, enabling the clock, and enabling the DDR controller.  Are there are any other dependencies that we should be aware of?

Thanks,

John Fielden

[naoumgitnik · Accepted solution]

Hello John,

As of now, the IC design team confirmed the "When power is stable, the memory controller automatically initializes the memory devices." statement from the Datasheet:

"DDR initialization is software-controlled, and it is mentioned in the Reference Manual that DDR initialization should happen once the power supplies for both controller and memory are stable. So board designer/customer would know the worst case time of DDR supply to stabilize, and he can insert as much delay as he wants in software."

In addition:

My Q.:

Please, provide answer for the 2 below sub-cases (not finalized yet in the design…):

1. the DDR memory chip powered from the same 1.5V rail as the Vybrid’s DDR controller,
2. the DDR memory chip already turned on way prior to 1.5V for the Vybrid’s DDR controller.

IC design team's A:

The only issue I see with DDR memory chip already turned on before Vybrid’s DDR controller is some extra leakage due to undriven pads to DDR memory until Vybrid controller gets power but I do not think this will result in any functional failures.

BTW, regarding enabling clocks I mentioned earlier - based on 'Figure 4. Power supply' in the Datasheet and the IC design team's information, 1.5V is only used for the level-shifted pads (pins), but the DDR controller, including its timing units, etc., is powered from the other Vybrid's power rails.

Regards, Naoum Gitnik.

[naoumgitnik]

Hello John,

• It looks like my approach works, right? And yes, in this case you save power on the Vybrid's DDR controller.
• I will forward your question to the Design team; expect reply within several business days.

Regards, Naoum Gitnik.

[timesyssupport]

Hello John,

Unfortunately, we are not aware of a way to reinitialize the DDR controller without performing a system reset.

Thanks, and let me know if you have any questions.

Timesys Support

[karina_valencia]

timesyssupport can you help on this case?