The Hardware Development Guide for Vybrid, Rev. 1, 05/2015 says in Table 20 on page 36 that the reference length for the DDR_CLK differential pair is 3 inches. Do they have to be this long? The Guide recommended that the traces be as short as possible in other places. Can we route the DDR_CLK differential pair 1 inch or 800 mils?
Also, what strategy does Table 22 on page 39 show, same-length or by-byte group? Thank you.
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There are two approaches:
- same length for all lines
- or matching by group (data slice).
3 inches is maximal length for same length 2.25 inches for group match. Shorter better. You should easily achieve 800mils.
There are common rules for DRAM/DDR3 memories which should be followed also here like:
- differential lines match
- match in each data slice (Data0, Data1, C/A)
- C/A lines < clock lines
The best way is to copy the reference design from TWR-VF65 rev.H which is available on the web. Vybrid VF6xx Tower System Kit with ARM DS-5|NXP